From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Tiago Martins Araújo" <tiago.martins.araujo@gmail.com>,
dri-devel@lists.freedesktop.org
Cc: airlied@gmail.com, simona@ffwll.ch
Subject: Re: DisplayID checksum validation blocking hardware capabilities - CSO T3 panel
Date: Mon, 15 Sep 2025 12:00:29 +0300 [thread overview]
Message-ID: <e164367cec1aaeaa00a065628b7ab72c3e12eaa5@intel.com> (raw)
In-Reply-To: <2da1034168eecf015640f84e6e1180b3ae1d3b94@intel.com>
On Mon, 15 Sep 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> That's not the complete EDID data, though. It's missing 6*16 bytes. If
> you go by the hex offsets, 0x100 does not follow 0x090.
Alternatively, there's extra garbage at the end. I'm not really sure
what happens because we have no logs, and we discard extension blocks
that fail the checksum. (This is something I've been meaning to change
no matter what; we shouldn't modify the EDID.)
--
Jani Nikula, Intel
prev parent reply other threads:[~2025-09-15 9:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-14 15:13 DisplayID checksum validation blocking hardware capabilities - CSO T3 panel Tiago Martins Araújo
2025-09-14 21:43 ` Dave Airlie
2025-09-15 9:24 ` Jani Nikula
2025-09-15 19:22 ` Tiago Martins Araújo
2025-10-28 19:08 ` Jani Nikula
2025-10-28 19:25 ` Tiago Martins Araújo
2025-10-28 20:09 ` Jani Nikula
2025-10-28 21:32 ` Tiago Martins Araújo
2025-10-30 10:51 ` Jani Nikula
2025-10-31 10:13 ` Jani Nikula
2025-10-31 10:42 ` Tiago Martins Araújo
2025-09-15 8:51 ` Jani Nikula
2025-09-15 9:00 ` Jani Nikula [this message]
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