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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df913dd8d2sm48984825ad.20.2026.09.28.18.45.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Sep 2026 18:45:10 -0700 (PDT) Message-ID: Date: Tue, 29 Sep 2026 09:45:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 7/7] drm/verisilicon: fix DC8200 primary plane disable clearing FB_EN To: Icenowy Zheng , maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260918030125.315978-1-a0987203069@gmail.com> <20260918030125.315978-8-a0987203069@gmail.com> <4a7b271d2a90eff94c27dec3bf24114ce44df1fd.camel@iscas.ac.cn> <1d988dfb-c930-4c17-ae77-47b93ff9f159@gmail.com> Content-Language: en-US From: Joey Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Icenowy Zheng 於 2026/9/26 下午 12:48 寫道: > 在 2026-09-25五的 22:55 +0800，Icenowy Zheng写道： >> 在 2026-09-21一的 15:49 +0800，Joey Lu写道： >>> Icenowy Zheng 於 2026/9/21 下午 03:30 寫道: >>>> Maybe it's better to just make it the 2nd patch in this patchset, >>>> just >>>> after the binding change. >>>> >>>> Waiting for something into drm-misc-fixes again will need another >>>> fixes >>>> pull and another RC back merge, which can consume weeks and miss >>>> the >>>> current merging window. >>>> >>>> In addition, it's possible that `drm/verisilicon: introduce per- >>>> variant >>>> hardware ops table` also gets backported for a more clean primary >>>> plane >>>> atomic_update disabling fix. >>> Understood. I'll fold the FB_EN fix in as patch 2, right after the >> Should I just apply this revision of patch with this reorder? > Oh I think more fixes are coming. > > There's one more DC8200-specific problem (which might be problematic on > DC8000 but I am not sure): The vs_dc8200_panel_disable_ex sequence must > be executed before vs_dc8200_panel_enable_ex, because some timing > parameters seem to be latched when the value going from 0 to 1, and > when a stale state is programmed before the driver is loaded (e.g. a > firmware driving the display) and the timing isn't the same with the > timing of the first modeset, the modeset will fail. > > I'm thinking about sending a fix patchset first, which will pick the > FB_EN fix here, implement a fix for the stale state problem and maybe > implement fixes for the old state dereference problems for hidden > planes in their atomic_update callback (although this fix will > introduce a helper, which will then be moved and renamed in the DC8200 > ops patch). > > Thanks, > Icenowy Understood, happy to hold the DCUltraLite series until your fix patchset lands, and rebase the ops-table patch on top of it then. On DC8000: its panel enable/disable path just toggles a plain FB_CONFIG_RESET bit, not the staged PANEL_CONFIG/PANEL_START latch registers DC8200 uses, so it doesn't look like it shares this specific ordering hazard from the register layout alone. I'll run the tests again after applying our variant on top of it. >> Thanks, >> Icenowy >> >>> dt-bindings patch, targeting the current vs_primary_plane.c >>> directly, >>> so the ops-table patch just carries the already-corrected code >>> forward >>> into vs_dc8200.c. Agreed that's faster than round-tripping. >>> >>> On primary_plane_disable_ex - I'll keep the "_ex" suffix. DC8200 >>> still >>> has a real per-variant operation there (clearing FB_EN + commit), >>> while >>> DC8000 leaves it NULL and does nothing, so the suffix still >>> reflects >>> an actual per-variant difference, not just structure introduced by >>> the >>> refactor. >>> >>> While testing the cursor plane, I found the same class of bug >>> there: >>> the disable register write was being triggered from the plane's >>> atomic_update() invisible-branch using the old plane state to look >>> up >>> the CRTC/output, which can be stale or NULL on a plane's very first >>> commit if it's already invisible then. I've fixed it locally by >>> having >>> atomic_update() derive the CRTC/output from the state it already >>> holds >>> before checking visibility, instead of falling through to the >>> old-state-based disable path. Just flagging it here for now - >>> vs_cursor_plane.c isn't touched by any of my patches. >>> >>> Thanks.