Re: [PATCH] accel/ivpu: Wait for CDYN de-assertion during power down sequence

[Karol Wachowski <karol.wachowski@linux.intel.com>]

On 10/29/2025 4:47 PM, Jeff Hugo wrote:
> On 10/28/2025 1:06 AM, Karol Wachowski wrote:
>> During power down, pending DVFS operations may still be in progress
>> when the NPU reset is asserted after CDYN=0 is set. Since the READY
>> bit may already be deasserted at this point, checking only the READY
>> bit is insufficient to ensure all transactions have completed.
>>
>> Add an explicit check for CDYN de-assertion after the READY bit check
>> to guarantee no outstanding transactions remain before proceeding.
>
> Is it worthwhile to mention what can break if transactions are pending
> while we proceed? Is there something that the user will see?
>
> I'm guessing that proceeding with active transactions is bad, but its
> unclear to me if this is just a best practice, or actually fixes some
> kind of issue that will actually impact the user.  If there is actual
> user impact that this addresses, should we consider a fixes tag?
>
> -Jeff 
Hi
Jeff,                                                                                                                                           

This is primarily a best practice to avoid potential issues on NPU6,
where pending transactions can cause issues with power down transition. 
While it doesn't fix user-visible bugs on existing platforms, it ensures
unified power down sequence across all platforms that support this
register, making the code clearer than conditional handling just for NPU6.

You're right about the Fixes tag, since NPU6 support is already
upstream, I'll add one.

-Karol