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dkim=none (message not signed) header.d=none; lists.freedesktop.org; dmarc=none action=none header.from=intel.com; Received: from CO6PR11MB5634.namprd11.prod.outlook.com (2603:10b6:5:35d::20) by CO6PR11MB5571.namprd11.prod.outlook.com (2603:10b6:5:35f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21; Wed, 21 Jul 2021 01:11:44 +0000 Received: from CO6PR11MB5634.namprd11.prod.outlook.com ([fe80::5d5e:b6bf:aafa:ecd4]) by CO6PR11MB5634.namprd11.prod.outlook.com ([fe80::5d5e:b6bf:aafa:ecd4%8]) with mapi id 15.20.4331.034; Wed, 21 Jul 2021 01:11:44 +0000 Subject: Re: [Intel-gfx] [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature To: Michal Wajdeczko , , References: <20210710012026.19705-1-vinay.belgaumkar@intel.com> <20210710012026.19705-17-vinay.belgaumkar@intel.com> <36320288-c921-007d-20db-c2b29812b968@intel.com> From: "Belgaumkar, Vinay" Message-ID: Date: Tue, 20 Jul 2021 18:11:41 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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Use a H2G message >> to tell guc to enable GUCRC. When disabling RC6, tell guc to > > s/GUC/GuC > s/guc/GuC Done. > >> revert RC6 control back to KMD. >> >> Signed-off-by: Vinay Belgaumkar >> --- >> drivers/gpu/drm/i915/Makefile | 1 + >> drivers/gpu/drm/i915/gt/intel_rc6.c | 22 ++++-- >> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++ >> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 + >> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 + >> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 79 +++++++++++++++++++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 32 ++++++++ >> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 + >> 8 files changed, 140 insertions(+), 5 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h >> >> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile >> index d8eac4468df9..3fc17f20d88e 100644 >> --- a/drivers/gpu/drm/i915/Makefile >> +++ b/drivers/gpu/drm/i915/Makefile >> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \ >> gt/uc/intel_guc_fw.o \ >> gt/uc/intel_guc_log.o \ >> gt/uc/intel_guc_log_debugfs.o \ >> + gt/uc/intel_guc_rc.o \ >> gt/uc/intel_guc_slpc.o \ >> gt/uc/intel_guc_submission.o \ >> gt/uc/intel_huc.o \ >> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c >> index 259d7eb4e165..299fcf10b04b 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c >> @@ -98,11 +98,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) >> set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); >> set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); >> >> - /* 3a: Enable RC6 */ >> - rc6->ctl_enable = >> - GEN6_RC_CTL_HW_ENABLE | >> - GEN6_RC_CTL_RC6_ENABLE | >> - GEN6_RC_CTL_EI_MODE(1); >> + /* 3a: Enable RC6 >> + * >> + * With GUCRC, we do not enable bit 31 of RC_CTL, >> + * thus allowing GuC to control RC6 entry/exit fully instead. >> + * We will not set the HW ENABLE and EI bits >> + */ >> + if (!intel_guc_rc_enable(>->uc.guc)) >> + rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; >> + else >> + rc6->ctl_enable = >> + GEN6_RC_CTL_HW_ENABLE | >> + GEN6_RC_CTL_RC6_ENABLE | >> + GEN6_RC_CTL_EI_MODE(1); >> >> pg_enable = >> GEN9_RENDER_PG_ENABLE | >> @@ -513,6 +521,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) >> { >> struct drm_i915_private *i915 = rc6_to_i915(rc6); >> struct intel_uncore *uncore = rc6_to_uncore(rc6); >> + struct intel_gt *gt = rc6_to_gt(rc6); >> + >> + /* Take control of RC6 back from GuC */ >> + intel_guc_rc_disable(>->uc.guc); >> >> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); >> if (GRAPHICS_VER(i915) >= 9) >> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h >> index 596cf4b818e5..2ddb9cdc0a59 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h >> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h >> @@ -136,6 +136,7 @@ enum intel_guc_action { >> INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008, >> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009, >> INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, >> + INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004, >> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, >> INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502, >> INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503, >> @@ -146,6 +147,11 @@ enum intel_guc_action { >> INTEL_GUC_ACTION_LIMIT >> }; >> >> +enum intel_guc_rc_options { >> + INTEL_GUCRC_HOST_CONTROL, >> + INTEL_GUCRC_FIRMWARE_CONTROL, >> +}; >> + >> enum intel_guc_preempt_options { >> INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, >> INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c >> index 82863a9bc8e8..0d55b24f7c67 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c >> @@ -158,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc) >> intel_guc_log_init_early(&guc->log); >> intel_guc_submission_init_early(guc); >> intel_guc_slpc_init_early(guc); >> + intel_guc_rc_init_early(guc); >> >> mutex_init(&guc->send_mutex); >> spin_lock_init(&guc->irq_lock); >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h >> index 0dbbd9cf553f..592d52e5e93c 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h >> @@ -59,6 +59,8 @@ struct intel_guc { >> >> bool submission_supported; >> bool submission_selected; >> + bool rc_supported; >> + bool rc_selected; >> bool slpc_supported; >> bool slpc_selected; >> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> new file mode 100644 >> index 000000000000..45b61432c56d >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c >> @@ -0,0 +1,79 @@ >> +// SPDX-License-Identifier: MIT >> +/* >> + * Copyright © 2020 Intel Corporation > > 2021 Done. > >> +*/ > > unaligned * done. > >> + >> +#include "intel_guc_rc.h" >> +#include "gt/intel_gt.h" >> +#include "i915_drv.h" >> + >> +static bool __guc_rc_supported(struct intel_guc *guc) >> +{ >> + /* GuC RC is unavailable for pre-Gen12 */ >> + return guc->submission_supported && >> + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12; >> +} >> + >> +static bool __guc_rc_selected(struct intel_guc *guc) >> +{ >> + if (!intel_guc_rc_is_supported(guc)) >> + return false; >> + >> + return guc->submission_selected; >> +} >> + >> +void intel_guc_rc_init_early(struct intel_guc *guc) >> +{ >> + guc->rc_supported = __guc_rc_supported(guc); >> + guc->rc_selected = __guc_rc_selected(guc); >> +} >> + >> +static int guc_action_control_gucrc(struct intel_guc *guc, bool enable) >> +{ >> + struct drm_device *drm = &guc_to_gt(guc)->i915->drm; >> + u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL : >> + INTEL_GUCRC_HOST_CONTROL; >> + u32 action[] = { >> + INTEL_GUC_ACTION_SETUP_PC_GUCRC, >> + rc_mode >> + }; >> + int ret; >> + >> + ret = intel_guc_send(guc, action, ARRAY_SIZE(action)); >> + if (ret) > > since intel_guc_send() may return non-zero value from data0 RESPONSE > field, assuming that this action expects there MBZ this should be: > > ret = ret > 0 ? -EPROTO : ret; > > otherwise some static code analyzers might complain > >> + drm_err(drm, "Failed to set GUCRC mode(%d), err=%d\n", > > you may want to print error with %pe > and move this message to __guc_rc_control because of the above Ok, done. > >> + rc_mode, ret); >> + >> + return ret; >> +} >> + >> +static int __guc_rc_control(struct intel_guc *guc, bool enable) >> +{ >> + struct intel_gt *gt = guc_to_gt(guc); >> + int ret; >> + >> + if (!intel_uc_uses_guc_rc(>->uc)) >> + return -ENOTSUPP; >> + >> + if (!intel_guc_is_ready(guc)) >> + return -EINVAL; >> + >> + ret = guc_action_control_gucrc(guc, enable); >> + if (unlikely(ret)) > > drm_err(drm, "Failed to %s GuC RC mode (%pe)\n", > enabledisable(enable), ERR_PTR(ret)); > >> + return ret; >> + >> + drm_info(>->i915->drm, "GuC RC %s\n", >> + enableddisabled(enable)); >> + >> + return 0; >> +} >> + >> +int intel_guc_rc_enable(struct intel_guc *guc) >> +{ >> + return __guc_rc_control(guc, true); >> +} >> + >> +int intel_guc_rc_disable(struct intel_guc *guc) >> +{ >> + return __guc_rc_control(guc, false); >> +} >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h >> new file mode 100644 >> index 000000000000..169e60726e5b >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h >> @@ -0,0 +1,32 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2020 Intel Corporation > > 2021 Done. > >> + */ >> + >> +#ifndef _INTEL_GUC_RC_H_ >> +#define _INTEL_GUC_RC_H_ >> + >> +#include > > do you need this include here ? guess not. Thanks, Vinay. > > Michal > >> +#include "intel_guc_submission.h" >> + >> +void intel_guc_rc_init_early(struct intel_guc *guc); >> + >> +static inline bool intel_guc_rc_is_supported(struct intel_guc *guc) >> +{ >> + return guc->rc_supported; >> +} >> + >> +static inline bool intel_guc_rc_is_wanted(struct intel_guc *guc) >> +{ >> + return guc->submission_selected && intel_guc_rc_is_supported(guc); >> +} >> + >> +static inline bool intel_guc_rc_is_used(struct intel_guc *guc) >> +{ >> + return intel_guc_submission_is_used(guc) && intel_guc_rc_is_wanted(guc); >> +} >> + >> +int intel_guc_rc_enable(struct intel_guc *guc); >> +int intel_guc_rc_disable(struct intel_guc *guc); >> + >> +#endif >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h >> index 38e465fd8a0c..29d8ad6d9087 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h >> @@ -7,6 +7,7 @@ >> #define _INTEL_UC_H_ >> >> #include "intel_guc.h" >> +#include "intel_guc_rc.h" >> #include "intel_guc_submission.h" >> #include "intel_huc.h" >> #include "i915_params.h" >> @@ -84,6 +85,7 @@ uc_state_checkers(guc, guc); >> uc_state_checkers(huc, huc); >> uc_state_checkers(guc, guc_submission); >> uc_state_checkers(guc, guc_slpc); >> +uc_state_checkers(guc, guc_rc); >> >> #undef uc_state_checkers >> #undef __uc_state_checker >>