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[2001:1c00:c0c:fe00:d2ea:f29d:118b:24dc]) by smtp.gmail.com with ESMTPSA id rp21sm13345743ejb.97.2020.06.09.06.45.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2020 06:45:25 -0700 (PDT) Subject: Re: [PATCH v2 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 To: Andy Shevchenko References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-7-hdegoede@redhat.com> <20200609112905.GK2428291@smile.fi.intel.com> From: Hans de Goede Message-ID: Date: Tue, 9 Jun 2020 15:45:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200609112905.GK2428291@smile.fi.intel.com> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, intel-gfx , "Rafael J . Wysocki" , linux-acpi@vger.kernel.org, Thierry Reding , dri-devel@lists.freedesktop.org, =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Mika Westerberg , Len Brown Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On 6/9/20 1:29 PM, Andy Shevchenko wrote: > On Sun, Jun 07, 2020 at 08:18:31PM +0200, Hans de Goede wrote: >> While looking into adding atomic-pwm support to the pwm-crc driver I >> noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and >> there is a clock-divider which divides this with a value between 1-128, >> and there are 256 duty-cycle steps. >> >> The pwm-crc code before this commit assumed that a clock-divider >> setting of 1 means that the PWM output is running at 6 MHZ, if that >> is true, where do these 256 duty-cycle steps come from? >> >> This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that >> seems unlikely for a PMIC which is using a silicon process optimized for >> power-switching transistors. It is way more likely that there is an 8 >> bit counter for the duty cycle which acts as an extra fixed divider >> wrt the PWM output frequency. >> >> The main user of the pwm-crc driver is the i915 GPU driver which uses it >> for backlight control. Lets compare the PWM register values set by the >> video-BIOS (the GOP), assuming the extra fixed divider is present versus >> the PWM frequency specified in the Video-BIOS-Tables: >> >> Device: PWM Hz set by BIOS PWM Hz specified in VBT >> Asus T100TA 200 200 >> Asus T100HA 200 200 >> Lenovo Miix 2 8 23437 20000 >> Toshiba WT8-A 23437 20000 >> >> So as we can see if we assume the extra division by 256 then the register >> values set by the GOP are an exact match for the VBT values, where as >> otherwise the values would be of by a factor of 256. >> >> This commit fixes the period / duty_cycle calculations to take the >> extra division by 256 into account. > > ... > >> +#define NSEC_PER_MHZ 1000 > > This is against physics. What this cryptic name means actually? > Existing NSEC_PER_USEC ? Yes, using existing NSEC_PER_USEC is better I will use that for the next version. Regards, Hans _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel