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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55a31d91134sm1959164e87.145.2025.07.22.06.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 06:49:02 -0700 (PDT) Date: Tue, 22 Jul 2025 16:49:00 +0300 From: Dmitry Baryshkov To: Akhil P Oommen Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/17] drm/msm: Add support for IFPC Message-ID: References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-11-9347aa5bcbd6@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250720-ifpc-support-v1-11-9347aa5bcbd6@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDExMyBTYWx0ZWRfX+hBq34Xhf+Ol jLGb1mlj6CyQ0Li7wBP+DezvLgdwQbmtP812L9UYzzpKhls5wnCilPZ0ySbtEsTqE62al91h5m0 La+kBF7aZZRsfd2H0dumDXlHpVBIsVLG5nSp2axYgZP6T/I9WNQoq1KOov3BUzTOvgNfV+8E25/ FbHwwhrXY3YF4wLSXwYlQflKWohrD5mhKC5/GAhRoVwx9qkNUGBkW1WlzC96LWuDkK8ZucjPbBf t2C3bKkBsfJMy9/Ae7onmrCwAW1jdT6fzSWo0+eqS/OgBRUBieaismJ5bwztlWaHWm7HV8dax21 c4djF7KEahJ/0c+rThkIads6UoHuonHIL1grNOry5U/4orhOEVS8XuBmNGTdDiYSUyxWLueB9Yg Hr+PM8ITRl4RzDony9aWCqUu5/hH+P3gqwTAf+ErZa/3fUsTmRvIrWcTxp9F/bS8ozLhZYmf X-Proofpoint-ORIG-GUID: fFtwoB0cZ15DJ7axDSMCzPg-1zC3wE4T X-Proofpoint-GUID: fFtwoB0cZ15DJ7axDSMCzPg-1zC3wE4T X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=687f96d0 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=i_i2Vd3NPHTucyE0f70A:9 a=CjuIK1q_8ugA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220113 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sun, Jul 20, 2025 at 05:46:12PM +0530, Akhil P Oommen wrote: > Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support > for a gpu. Based on this flag send the feature ctrl hfi message to > GMU to enable IFPC support. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++-- > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 +++++++++++++++++++++++++++------ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 3 files changed, 31 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 4d6c70735e0892ed87d6a68d64f24bda844e5e16..3bbcc78179c1cf1bfa21ff097e9350eb2f554011 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -1961,8 +1961,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > if (ret) > return ret; > > - /* Fow now, don't do anything fancy until we get our feet under us */ > - gmu->idle_level = GMU_IDLE_STATE_ACTIVE; > + /* Set GMU idle level */ > + gmu->idle_level = (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ? > + GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE; > > pm_runtime_enable(gmu->dev); > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index 8e69b1e8465711837151725c8f70e7b4b16a368e..20ade6b0558b016b581078f5cf7377e7e7c57f8e 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -21,6 +21,7 @@ static const char * const a6xx_hfi_msg_id[] = { > HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE), > HFI_MSG_ID(HFI_H2F_MSG_TEST), > HFI_MSG_ID(HFI_H2F_MSG_START), > + HFI_MSG_ID(HFI_H2F_FEATURE_CTRL), > HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START), > HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE), > HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER), > @@ -765,23 +766,39 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) > NULL, 0); > } > > +static int a6xx_hfi_feature_ctrl_msg(struct a6xx_gmu *gmu, u32 feature, u32 enable, u32 data) > +{ > + struct a6xx_hfi_msg_feature_ctrl msg = { > + .feature = feature, > + .enable = enable, > + .data = data, > + }; > + > + return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0); > +} > + > +#define HFI_FEATURE_IFPC 9 Can we please have an enum or at least a set of defines rather than havign them scattered through the code? > + > +static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu) > +{ > + if (gmu->idle_level != GMU_IDLE_STATE_IFPC) > + return 0; > + > + return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, 0x1680); magic number? > +} > + > #define HFI_FEATURE_ACD 12 > > static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) > { > struct a6xx_hfi_acd_table *acd_table = &gmu->acd_table; > - struct a6xx_hfi_msg_feature_ctrl msg = { > - .feature = HFI_FEATURE_ACD, > - .enable = 1, > - .data = 0, > - }; > int ret; > > if (!acd_table->enable_by_level) > return 0; > > /* Enable ACD feature at GMU */ > - ret = a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0); > + ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_ACD, 1, 0); > if (ret) { > DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret); > return ret; > @@ -898,6 +915,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state) > if (ret) > return ret; > > + ret = a6xx_hfi_enable_ifpc(gmu); > + if (ret) > + return ret; > + > ret = a6xx_hfi_send_core_fw_start(gmu); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index bc063594a359ee6b796381c5fd2c30e2aa12a26d..1135beafac464f3162a3a61938a7de0c7920455a 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -58,6 +58,7 @@ enum adreno_family { > #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) > #define ADRENO_QUIRK_PREEMPTION BIT(5) > #define ADRENO_QUIRK_4GB_VA BIT(6) > +#define ADRENO_QUIRK_IFPC BIT(7) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > > -- > 2.50.1 > -- With best wishes Dmitry