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charset=UTF-8 Date: Wed, 12 Aug 2026 23:48:07 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "Daniel Almeida" , "Miguel Ojeda" , "Boqun Feng" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "Tamir Duberstein" , =?utf-8?q?Onur_=C3=96zkan?= , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , , , Subject: Re: [PATCH v2 12/16] gpu: nova-core: use projection for PFALCON and PFALCON2 registers From: "Alexandre Courbot" To: "Gary Guo" Content-Transfer-Encoding: quoted-printable References: <20260805-typed_register-v2-0-c3ca142220a0@garyguo.net> <20260805-typed_register-v2-12-c3ca142220a0@garyguo.net> In-Reply-To: <20260805-typed_register-v2-12-c3ca142220a0@garyguo.net> X-ClientProxiedBy: TY4P286CA0128.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:37f::17) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: driver-core@lists.linux.dev List-Id: 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HUaUb7RHLSkMwanM9ENamJ18ecMBULmKtKOEYpBghr37D8krXOq10dnokGESGSUVTSP36fN+Zltz1K4CeBqAPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8406 On Thu Aug 6, 2026 at 1:35 AM JST, Gary Guo wrote: > Add fixed size region types `PFalconRegisters` and `PFalcon2Registers` an= d > update PFALCON and PFALCON registers to be fixed register on them and not nit: second `PFALCON` should be `PFALCON2`. > relative registers on `NovaRegisters`. > > Update `Falcon` struct to store projected views when constructing and > access with `self.pfalcon` and `self.pfalcon2`. > > Signed-off-by: Gary Guo > --- > drivers/gpu/nova-core/falcon.rs | 157 +++++++++------= ------ > drivers/gpu/nova-core/falcon/fsp.rs | 63 +++++---- > drivers/gpu/nova-core/falcon/gsp.rs | 51 ++++--- > drivers/gpu/nova-core/falcon/hal/ga102.rs | 62 ++++---- > drivers/gpu/nova-core/falcon/hal/tu102.rs | 9 +- > drivers/gpu/nova-core/falcon/sec2.rs | 37 +++-- > drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 18 +-- > drivers/gpu/nova-core/gsp/hal/tu102.rs | 7 +- > drivers/gpu/nova-core/regs.rs | 91 ++++++------ > 9 files changed, 238 insertions(+), 257 deletions(-) > > diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falc= on.rs > index a91cbdd5d636..ed52572690ff 100644 > --- a/drivers/gpu/nova-core/falcon.rs > +++ b/drivers/gpu/nova-core/falcon.rs > @@ -14,13 +14,12 @@ > }, > io::{ > poll::read_poll_timeout, > - register::{ > - RegisterBase, > - WithBase, // > - }, > + register::Array, > Io, > + Mmio, // > }, > prelude::*, > + sizes::SZ_4K, > time::Delta, > }; > =20 > @@ -165,18 +164,22 @@ pub(crate) enum FalconFbifMemType with From> { > } > } > =20 > -/// Type used to represent the `PFALCON` registers address base for a gi= ven falcon engine. > -pub(crate) struct PFalconBase(()); > +/// Type used to represent the `PFALCON` registers. > +#[repr(align(4))] > +#[derive(FromBytes, IntoBytes)] > +pub(crate) struct PFalconRegisters([u8; SZ_4K]); > =20 > -/// Type used to represent the `PFALCON2` registers address base for a g= iven falcon engine. > -pub(crate) struct PFalcon2Base(()); > +/// Type used to represent the `PFALCON2` registers. > +#[repr(align(4))] > +#[derive(FromBytes, IntoBytes)] > +pub(crate) struct PFalcon2Registers([u8; SZ_4K]); > =20 > /// Trait defining the parameters of a given Falcon engine. > /// > /// Each engine provides one base for `PFALCON` and `PFALCON2` registers= . > -pub(crate) trait FalconEngine: > - Send + Sync + RegisterBase + RegisterBase= + Sized > -{ > +pub(crate) trait FalconEngine: Send + Sync + Sized { > + fn pfalcon(io: Bar0<'_>) -> Mmio<'_, PFalconRegisters>; > + fn pfalcon2(io: Bar0<'_>) -> Mmio<'_, PFalcon2Registers>; Remember on v1 when we contemplated using associated consts? Turns out we can with this version: // Need a better name, but you get the idea. pub(crate) type PFalconRegs =3D OffsetLoc; pub(crate) type PFalcon2Regs =3D OffsetLoc; pub(crate) trait FalconEngine: Send + Sync + Sized { const PFALCON: PFalconRegs; const PFALCON2: PFalcon2Regs; } ... and make `Falcon::new` call `io_project` directly, and it works! At the cost of importing `OffsetLoc` in `falcon.rs`, but that removes ~30 LoCs in total, and I'm not sure `OffsetLoc` should be hidden anyway. > } > =20 > /// Represents a portion of the firmware to be loaded into a particular = memory (e.g. IMEM or DMEM) > @@ -358,6 +361,8 @@ pub(crate) struct Falcon<'a, E: FalconEngine> { > hal: KBox>, > dev: &'a device::Device, > bar: Bar0<'a>, > + pub(crate) pfalcon: Mmio<'a, PFalconRegisters>, > + pfalcon2: Mmio<'a, PFalcon2Registers>, > } > =20 > impl<'a, E: FalconEngine + 'static> Falcon<'a, E> { > @@ -371,19 +376,19 @@ pub(crate) fn new( > hal: hal::falcon_hal(chipset)?, > dev, > bar, > + pfalcon: E::pfalcon(bar), > + pfalcon2: E::pfalcon2(bar), > }) > } > =20 > /// Resets DMA-related registers. > pub(crate) fn dma_reset(&self) { > - self.bar.update(regs::NV_PFALCON_FBIF_CTL::of::(), |v| { > + self.pfalcon.update(regs::NV_PFALCON_FBIF_CTL, |v| { > v.with_allow_phys_no_ctx(true) > }); > =20 > - self.bar.write( > - WithBase::of::(), > - regs::NV_PFALCON_FALCON_DMACTL::zeroed(), > - ); > + self.pfalcon > + .write_reg(regs::NV_PFALCON_FALCON_DMACTL::zeroed()); Remembering the debates we had over how to address relative registers when we ported registers to the new I/O scheme, I guess this new syntax which should make everyone happy! :) <...> > diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/= falcon/gsp.rs > index ae32f401aeb0..cbea6d7b49d3 100644 > --- a/drivers/gpu/nova-core/falcon/gsp.rs > +++ b/drivers/gpu/nova-core/falcon/gsp.rs > @@ -2,23 +2,24 @@ > =20 > use kernel::{ > io::{ > + io_project, > poll::read_poll_timeout, > - register::{ > - RegisterBase, > - WithBase, // > - }, > + register, > Io, > + Mmio, // > }, > prelude::*, > time::Delta, // > }; > =20 > use crate::{ > + driver::{ > + Bar0, > + NovaRegisters, // > + }, > falcon::{ > Falcon, > - FalconEngine, > - PFalcon2Base, > - PFalconBase, // > + FalconEngine, // > }, > regs, > }; > @@ -26,24 +27,31 @@ > /// Type specifying the `Gsp` falcon engine. Cannot be instantiated. > pub(crate) struct Gsp(()); > =20 > -impl RegisterBase for Gsp { > - const BASE: usize =3D 0x00110000; > -} > +register! { > + base: NovaRegisters; > =20 > -impl RegisterBase for Gsp { > - const BASE: usize =3D 0x00111000; > + PFALCON: super::PFalconRegisters @ 0x00110000; > + PFALCON2: super::PFalcon2Registers @ 0x00111000; > } > =20 > -impl FalconEngine for Gsp {} > +impl FalconEngine for Gsp { > + #[inline] > + fn pfalcon<'a>(io: Bar0<'a>) -> Mmio<'a, super::PFalconRegisters> { > + io_project!(io, build: PFALCON) > + } > + > + #[inline] > + fn pfalcon2<'a>(io: Bar0<'a>) -> Mmio<'a, super::PFalcon2Registers> = { The lifetime `'a` is elided in `fsp.rs` and `sec2.rs`, so we can also do it here. But the point is moot if we switch to associated consts anyway. > + io_project!(io, build: PFALCON2) > + } > +} > =20 > impl<'a> Falcon<'a, Gsp> { > /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register = to > /// allow GSP to signal CPU for processing new messages in message q= ueue. > pub(crate) fn clear_swgen0_intr(&self) { > - self.bar.write( > - WithBase::of::(), > - regs::NV_PFALCON_FALCON_IRQSCLR::zeroed().with_swgen0(true), > - ); > + self.pfalcon > + .write_reg(regs::NV_PFALCON_FALCON_IRQSCLR::zeroed().with_sw= gen0(true)); > } > =20 > /// Checks if GSP reload/resume has completed during the boot proces= s. > @@ -59,8 +67,8 @@ pub(crate) fn check_reload_completed(&self, timeout: De= lta) -> Result { > =20 > /// Returns whether the RISC-V branch privilege lockdown bit is set. > pub(crate) fn riscv_branch_privilege_lockdown(&self) -> bool { > - self.bar > - .read(regs::NV_PFALCON_FALCON_HWCFG2::of::()) > + self.pfalcon > + .read(regs::NV_PFALCON_FALCON_HWCFG2) > .riscv_br_priv_lockdown() > } > =20 > @@ -71,10 +79,7 @@ pub(crate) fn priv_target_mask_released(&self) -> bool= { > const LOCKED_PATTERN: u32 =3D 0xbadf_4100; > const LOCKED_MASK: u32 =3D 0xffff_ff00; > =20 > - let hwcfg2 =3D self > - .bar > - .read(regs::NV_PFALCON_FALCON_HWCFG2::of::()) > - .into_raw(); > + let hwcfg2 =3D self.pfalcon.read(regs::NV_PFALCON_FALCON_HWCFG2)= .into_raw(); > =20 > hwcfg2 !=3D 0 && (hwcfg2 & LOCKED_MASK) !=3D LOCKED_PATTERN > } > diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova= -core/falcon/hal/ga102.rs > index 7600ee07ca2e..ebfaff3d960f 100644 > --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs > +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs > @@ -6,11 +6,9 @@ > device, > io::{ > poll::read_poll_timeout, > - register::{ > - Array, > - WithBase, // > - }, > - Io, // > + register::Array, > + Io, > + Mmio, // > }, > prelude::*, > time::Delta, // > @@ -24,6 +22,7 @@ > FalconBromParams, > FalconEngine, > FalconModSelAlgo, > + PFalcon2Registers, > PeregrineCoreSelect, // > }, > regs, > @@ -31,17 +30,16 @@ > =20 > use super::FalconHal; > =20 > -fn select_core_ga102(bar: Bar0<'_>) -> Result { > - let bcr_ctrl =3D bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::())= ; > +fn select_core_ga102(pfalcon2: Mmio<'_, PFalcon2Registe= rs>) -> Result { The generic parameter `E` is now unused and can be removed. > + let bcr_ctrl =3D pfalcon2.read(regs::NV_PRISCV_RISCV_BCR_CTRL); > if bcr_ctrl.core_select() !=3D PeregrineCoreSelect::Falcon { > - bar.write( > - WithBase::of::(), > + pfalcon2.write_reg( > regs::NV_PRISCV_RISCV_BCR_CTRL::zeroed().with_core_select(Pe= regrineCoreSelect::Falcon), > ); > =20 > // TIMEOUT: falcon core should take less than 10ms to report bei= ng enabled. > read_poll_timeout( > - || Ok(bar.read(regs::NV_PRISCV_RISCV_BCR_CTRL::of::())), > + || Ok(pfalcon2.read(regs::NV_PRISCV_RISCV_BCR_CTRL)), > |r| r.valid(), > Delta::ZERO, > Delta::from_millis(10), > @@ -86,24 +84,23 @@ fn signature_reg_fuse_version_ga102( > Ok(u16::BITS - reg_fuse_version.leading_zeros()) > } > =20 > -fn program_brom_ga102(bar: Bar0<'_>, params: &FalconBro= mParams) { > - bar.write( > - WithBase::of::().at(0), > +fn program_brom_ga102( Same here. <...> > @@ -359,7 +356,7 @@ pub(crate) fn usable_fb_size(self) -> u64 { > 25:25 aincr =3D> bool; > } > =20 > - pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 { > + pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ 0x00000ac4 { > 31:0 data =3D> u32; > } > } > @@ -385,13 +382,13 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem)= -> Self { > =20 > impl NV_PFALCON_FALCON_ENGINE { > /// Resets the falcon > - pub(crate) fn reset_engine(bar: Bar0<'_>) { > - bar.update(Self::of::(), |r| r.with_reset(true)); > + pub(crate) fn reset_engine(pfalcon: Mmio<'_, PFalco= nRegisters>) { Here as well `E` can be dropped.