Re: [PATCH RFC 1/2] dt-bindings: regmap: add common schema for no-sequential-read

[Richard Leitner <richard.leitner@linux.dev>]

On Wed, Jul 22, 2026 at 11:16:22PM +0300, Laurent Pinchart wrote:
> On Wed, Jul 22, 2026 at 08:24:37PM +0200, Richard Leitner wrote:
> > On Wed, Jul 22, 2026 at 02:59:12PM +0100, Mark Brown wrote:
> > > On Wed, Jul 22, 2026 at 10:42:46AM +0200, Richard Leitner wrote:
> > > > Introduce a common regmap dt-binding schema with an optional boolean
> > > > property no-sequential-read to describe hardware integrations where
> > > > reading multiple consecutive registers in a single operation is not
> > > > reliable and registers must be read individually.
> > > 
> > > > A typical case are imaging sensors used on vendor-provided camera
> > > > modules whose bus integration does not support reads that advance across
> > > > consecutive register addresses. In such cases, single-register reads
> > > > work, but bulk reads do not. This restriction is a property of the
> > > > concrete hardware integration, not of the chip itself. It therefore
> > > > cannot be identified from the device driver and duplicating firmware
> > > > parsing in each affected driver does not scale.
> > > 
> > > No, this should not be a DT property.  We should discover this through
> > > the bus, just like we do currently for the various I2C quirks that are
> > > advertied by the I2C subsystem.
> > 
> > What do you mean "discover this through the bus"? As mentioned in the
> > commit message there is no possibility to detect that within the affected
> > I2C device drivers.
> > 
> > Or do you mean that it should be "discovered" by modelling the MCU which
> > "proxies" the I2C traffic between the host and the sensor/device as some
> > kind of "parent" device of the sensor?
> 
> Mark's comment wasn't totally clear to me. I think this is what he
> meant.
> 
> Richard, do you know if the MCU (which is actually an FPGA if I'm not
> mistaken) intercepts the I2C signals (i.e. is interposed between the
> host and the image sensor), or is "just" connected on the same I2C bus
> and messes up the I2C transfer when it detects a condition it dislikes
> (for instance by pulling the SDA line down when it detects a read from a
> protected register) ?

Tbh. I don't know. The VC MIPI Camera Module Hardware Operating manual
suggests both, the controller and the sensor sit on the same I2C bus:

https://www.mipi-modules.com/fileadmin/external/documentation/hardware/VC_MIPI_Camera_Module/index.html#mipi-sensor-module-circuit

But that's just a block diagram and nothing is written down really.

I tried some reverse-engineering and probed most of the accessible pads
of the camera module with my scope. I found no evidence that there is "a
second I2C bus" with "delayed" signals as I would suspect if the FPGA
really intercepts the I2C traffic.

Nonetheless this is by far no proof that this isn't the case, as the I2C
lanes of the imaging sensor are not accessible without destroying the PCB
:-(

So any help/feedback/information is greatly appreciated.


@Mark: I understood that if the fpga really intercepts the I2C bus, it
should be modelled accordingly in device tree. But what would be the
preferred implementation if both devices sit on the same I2C bus, but
one is messing up some register reads on purpose?

thanks & regards;rl

> 
> > Or something other?
> > 
> > Sorry, if I don't get it, but currently I see no other option than
> > providing this information somehow via device-tree. No matter if it's in
> > regmap or I2C.
> 
> -- 
> Regards,
> 
> Laurent Pinchart