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Wed, 28 Oct 2026 11:38:22 -0700 Received: from nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Wed, 28 Oct 2026 11:38:18 -0700 Date: Wed, 28 Oct 2026 11:38:15 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Shameer Kolothum Thodi , Catalin Marinas , Will Deacon , "joro@8bytes.org" , Robin Murphy , "rafael@kernel.org" , Danilo Krummrich , Marek Szyprowski , "aneesh.kumar@kernel.org" , Mark Rutland , "Greg Kroah-Hartman" , Suzuki K Poulose , Gavin Shan , Vikram Sethi , Anshuman Khandual , "Shanker Donthineni" , Mostafa Saleh , "rppt@kernel.org" , Thomas Huth , "Marc Zyngier" , Ryan Roberts , "kas@kernel.org" , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , Florian Fainelli , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "driver-core@lists.linux.dev" , Sonang Patel , "Ankit Agrawal" Subject: Re: [PATCH v1 2/8] firmware: arm_rmm: Add VSMMU commands and fields Message-ID: References: <0623345baaf550da1339e040b59f1fda902e3390.1789010941.git.nicolinc@nvidia.com> <20261028123509.GA2541714@nvidia.com> X-Mailing-List: driver-core@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 39nW9CcZU30sFE6Kv9+c16GJ0esMqMo2XltfPwNodnz6oMoKndc6lXKfiJl04hJOazSFX1J40AQozffjKnWggl1PStZxDggG9Y95fBkztvB17cQII7IBKyOoWRaAPmtaZO8ZKeYh6BfrHoFAWzhplmfcGxePV7VpTsEImnZQsV6IAoYe76pmONj3vDBBN8h43RwSdVEqrHtrz8W0cJzix+RzUh0AphIC4Hodr9p0TWTShvPF6mmJ7vlrNfdkvYULvyAHw3Imwc7XvzkdD9zPQRV2zshbrinwVzR1oOPEUxO/CKm++XCbnEduSSXncECZlWyay+4NspsIvVz28+s9U7oh87r2/Y+JSiBR2AjpG6w+AB1WGFV7ra8tN1ECPCAqcXOwdvw9INfbqeNyr/80j+r4tHpgq23bUHjhEtaBcO24Gp0Ul+YEPkEoXt2pUMLo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2026 18:38:47.7924 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a169a619-6bad-41d4-5bfc-08df3522b444 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL2PEPF000352CA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8974 On Wed, Oct 28, 2026 at 09:35:09AM -0300, Jason Gunthorpe wrote: > On Wed, Oct 28, 2026 at 09:49:53AM +0000, Shameer Kolothum Thodi wrote: > > > +static inline unsigned long rsi_arch_dev_activate(phys_addr_t base, > > > + unsigned long dev_type) > > > +{ > > > + struct arm_smccc_res res; > > > + > > > + arm_smccc_1_1_invoke(SMC_RSI_ARCH_DEV_ACTIVATE, base, > > > dev_type, &res); > > > > These calls leave unused input registers unspecified, whereas > > DEN0137 bet3 B1.2 marks them SBZ. Could we explicitly zero them? > > > > "On calling an RMI or RSI command, any of X1- X16 which are not > > specified as input values in the command definition SBZ" > > That seems too broad, Linux doesn't even support the x8-x16 inputs in > the macros. I think the spec has errd here. > > Requiring zeroing of x0-x7 is sort of reasonable. Any future use of > x8-x16 (including outputs) should require a direct opt in of the OS to > indicate it supports this bank of registers. > > Otherwise you probably need a new macro helper for this protocol.. We could probably replace it with: arm_smccc_smc(SMC_RSI_ARCH_DEV_ACTIVATE, base, dev_type, 0, 0, 0, 0, 0, &res); This should specify those unused inputs. Nicolin