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Wed, 28 Oct 2026 11:51:44 -0700 Received: from nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Wed, 28 Oct 2026 11:51:40 -0700 Date: Wed, 28 Oct 2026 11:51:38 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Shameer Kolothum Thodi , Catalin Marinas , Will Deacon , "joro@8bytes.org" , Robin Murphy , "rafael@kernel.org" , Danilo Krummrich , Marek Szyprowski , "aneesh.kumar@kernel.org" , Mark Rutland , "Greg Kroah-Hartman" , Suzuki K Poulose , Gavin Shan , Vikram Sethi , Anshuman Khandual , "Shanker Donthineni" , Mostafa Saleh , "rppt@kernel.org" , Thomas Huth , "Marc Zyngier" , Ryan Roberts , "kas@kernel.org" , Kohei Enju , Shaopeng Tan , Ard Biesheuvel , James Morse , Steven Price , Sang-Heon Jeon , Omar Sandoval , Andrew Morton , Jinjie Ruan , Sam Edwards , Douglas Anderson , Florian Fainelli , Chen-Yu Tsai , Huacai Chen , Thomas Zimmermann , Pranjal Shrivastava , Ashish Mhetre , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "driver-core@lists.linux.dev" , Sonang Patel , "Ankit Agrawal" Subject: Re: [PATCH v1 7/8] iommu: Park TDISP T=0 devices in the blocking domain Message-ID: References: <0d57c59aa3cae891e9d3e07e939e13918a4e99a0.1789010941.git.nicolinc@nvidia.com> <20261028150909.GC3040767@nvidia.com> X-Mailing-List: driver-core@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +sGuwxy+2QHT/AuT6K4mAFXJDJoRLWBohshkps7/FWCHIlypRaXPwWMZ6SBlo77Yv1NGeW9AjIFwKg3jH4b9TIDW67KW2ZZ7ugJK4ayu6s5OZL150nANpUxz+oaa3oswizJtkD4/mfKPtX4vzfJChoUsPJaXe9Tlt3oonU6Hb5Nz5+YHFXhqNRxiaEC1nAaaCg8Hh3T888VzZKaYAf1S69kXrQcfbSyzDUw8NQjvbaFjwZ0qpIlK/xZMd+ynehjjMiEXkMwUREssbmaiCzYP6NIlqE0sTh7zwc0d59JKhe8Bt/s+N+BhXrKjQRnYkurDxL6W840XaS4mfxF6Tpv8tebVAdKJmGT3SROZehbxd9zvLf1zhFJMQqZJ6MlbCgA4PSOKoHnWpB01MxMTJMCudiNnB/QI0GPXRJZCDmQCUgEPnx63qGaNJC+Enf+tw46o X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2026 18:52:03.3440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c110140f-03b3-46fd-8a6b-08df35248e6b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY7PEPF000000EB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9533 On Wed, Oct 28, 2026 at 12:09:09PM -0300, Jason Gunthorpe wrote: > On Wed, Oct 28, 2026 at 02:19:17PM +0000, Shameer Kolothum Thodi wrote: > > > + /* > > > + * When in T=0 mode the T=1 vIOMMU must always be set to > > > BLOCKED to > > > + * release control of ATS. > > > + */ > > > + if (iommu_using_t0_stream(first)) { > > > + if (!ops->blocked_domain) > > > + return ERR_PTR(-EINVAL); > > > + return ops->blocked_domain; > > > > How is MSI allocation handled for T=0 devices? The ITS calls > > iommu_dma_prepare_msi(), which appears to return -EOPNOTSUPP > > for the blocked domain. Is that intentional? > > For a TDISP capable devince MSI is always issued using T=0, meaning it > does not go through the SMMU. It should be wired to defeat > iommu_dma_prepare_msi() and use an identity IOVA as though there is no > iommu present.. I'll fold this in: ------------------------------------------------------------ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index d6b00e0373f5c..1474224c2565f 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -4324,8 +4324,9 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) return 0; mutex_lock(&group->mutex); - /* An IDENTITY domain must pass through */ - if (group->domain && group->domain->type != IOMMU_DOMAIN_IDENTITY) { + /* An IDENTITY domain or a T=0 device must pass through */ + if (group->domain && group->domain->type != IOMMU_DOMAIN_IDENTITY && + !iommu_using_t0_stream(dev)) { switch (group->domain->cookie_type) { case IOMMU_COOKIE_DMA_MSI: case IOMMU_COOKIE_DMA_IOVA: ------------------------------------------------------------ Thanks Nicolin