From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Torvalds Subject: Re: [PATCH 0/7] block-sha1: improved SHA1 hashing Date: Thu, 6 Aug 2009 17:13:04 -0700 (PDT) Message-ID: References: <4A7B1166.8020507@gmail.com> <4A7B2A88.2040602@gmail.com> <4A7B384C.2020407@gmail.com> <4A7B4D84.80906@gmail.com> <4A7B509A.5010405@gmail.com> <4A7B5F4C.30102@gmail.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Cc: Git Mailing List To: Artur Skawina X-From: git-owner@vger.kernel.org Fri Aug 07 02:13:27 2009 Return-path: Envelope-to: gcvg-git-2@gmane.org Received: from vger.kernel.org ([209.132.176.167]) by lo.gmane.org with esmtp (Exim 4.50) id 1MZD5K-0005dF-GI for gcvg-git-2@gmane.org; Fri, 07 Aug 2009 02:13:26 +0200 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756580AbZHGANI (ORCPT ); Thu, 6 Aug 2009 20:13:08 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754670AbZHGANI (ORCPT ); Thu, 6 Aug 2009 20:13:08 -0400 Received: from smtp1.linux-foundation.org ([140.211.169.13]:59709 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754017AbZHGANH (ORCPT ); Thu, 6 Aug 2009 20:13:07 -0400 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n770D4Lq021596 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 6 Aug 2009 17:13:06 -0700 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n770D4vI021340; Thu, 6 Aug 2009 17:13:04 -0700 X-X-Sender: torvalds@localhost.localdomain In-Reply-To: User-Agent: Alpine 2.01 (LFD 1184 2008-12-16) X-Spam-Status: No, hits=-3.966 required=5 tests=AWL,BAYES_00,OSDL_HEADER_SUBJECT_BRACKETED X-Spam-Checker-Version: SpamAssassin 3.2.4-osdl_revision__1.47__ X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Sender: git-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: git@vger.kernel.org Archived-At: On Thu, 6 Aug 2009, Linus Torvalds wrote: > > In particular, I'm thinking about the warnign in the intel optimization > manual: > > The rotate by immediate and rotate by register instructions are > more expensive than a shift. The rotate by 1 instruction has the > same latency as a shift. > > so it's very possible that "rotate by 1" is much better than other > rotates. Hmm. Probably not. Googling more seems to indicate that rotates and shifts have a fixed 4-cycle latency on Northwood. I'm not seeing anything that indicates that a single-bit rotate/shift would be any faster. (And remember, if 4 cycles doesn't sound so bad: that's enough of a latency to do _16_ "simple" ALU's, since they can be double-pumped in the two regular ALU's). I think long-running ALU ops that feed into a store (spill) also happen to be the thing that makes the dreaded store-buffer replay trap nasties happen more (load vs store scheduled badly, and then you end up spending tens of cycles just replaying). Linus