* 8250 memory mapped UART
@ 2017-03-01 5:53 Gailu Singh
2017-03-01 6:15 ` Fwd: " Gailu Singh
0 siblings, 1 reply; 15+ messages in thread
From: Gailu Singh @ 2017-03-01 5:53 UTC (permalink / raw)
To: grub-devel
[-- Attachment #1: Type: text/plain, Size: 343 bytes --]
Hi Experts,
I am using GRUB2 on intel apollo lake board. This board does not have IO
mapped uart instead it has 8250 memory mapped UART.
GRUB2 does not recognize memory mapped uart and gives error ("serial port
COM0 not found). There is a 8250 memory mapped driver available in
coreboot. Is it possible to port that driver to Grub2?
Thanks
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^ permalink raw reply [flat|nested] 15+ messages in thread* Fwd: 8250 memory mapped UART 2017-03-01 5:53 8250 memory mapped UART Gailu Singh @ 2017-03-01 6:15 ` Gailu Singh 2017-03-01 7:00 ` Andrei Borzenkov 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-01 6:15 UTC (permalink / raw) To: grub-devel [-- Attachment #1: Type: text/plain, Size: 343 bytes --] Hi Experts, I am using GRUB2 on intel apollo lake board. This board does not have IO mapped uart instead it has 8250 memory mapped UART. GRUB2 does not recognize memory mapped uart and gives error ("serial port COM0 not found). There is a 8250 memory mapped driver available in coreboot. Is it possible to port that driver to Grub2? Thanks [-- Attachment #2: Type: text/html, Size: 502 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 6:15 ` Fwd: " Gailu Singh @ 2017-03-01 7:00 ` Andrei Borzenkov 2017-03-01 9:38 ` Matthias Lange 0 siblings, 1 reply; 15+ messages in thread From: Andrei Borzenkov @ 2017-03-01 7:00 UTC (permalink / raw) To: The development of GNU GRUB, gailu96; +Cc: matthias.lange please test patches from Matthias Lange https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com> wrote: > Hi Experts, > > I am using GRUB2 on intel apollo lake board. This board does not have IO > mapped uart instead it has 8250 memory mapped UART. > > GRUB2 does not recognize memory mapped uart and gives error ("serial port > COM0 not found). There is a 8250 memory mapped driver available in coreboot. > Is it possible to port that driver to Grub2? > > Thanks > > > _______________________________________________ > Grub-devel mailing list > Grub-devel@gnu.org > https://lists.gnu.org/mailman/listinfo/grub-devel > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 7:00 ` Andrei Borzenkov @ 2017-03-01 9:38 ` Matthias Lange 2017-03-01 9:51 ` Gailu Singh 0 siblings, 1 reply; 15+ messages in thread From: Matthias Lange @ 2017-03-01 9:38 UTC (permalink / raw) To: Andrei Borzenkov, The development of GNU GRUB, gailu96 Hi, On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > please test patches from Matthias Lange > > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com> wrote: >> Hi Experts, >> >> I am using GRUB2 on intel apollo lake board. This board does not have IO >> mapped uart instead it has 8250 memory mapped UART. Could you share some details about the board? >> GRUB2 does not recognize memory mapped uart and gives error ("serial port >> COM0 not found). There is a 8250 memory mapped driver available in coreboot. >> Is it possible to port that driver to Grub2? My patch set adds support for 8250 MMIO PCI cards. Is the UART on your board connected via PCI? Best, Matthias. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 9:38 ` Matthias Lange @ 2017-03-01 9:51 ` Gailu Singh 2017-03-01 9:57 ` Gailu Singh 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-01 9:51 UTC (permalink / raw) To: Matthias Lange; +Cc: Andrei Borzenkov, The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 1244 bytes --] My board is Intel Oxbohill CRB (Apollo lake). On my board UART are not connected to PCI. I am using grub2 payload loaded by coreboot. UART works fine in coreboot by using memory mapped 8050 driver ( https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c), however when grub2 is loaded it refuses to recognize UART. On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange < matthias.lange@kernkonzept.com> wrote: > Hi, > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > please test patches from Matthias Lange > > > > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com> wrote: > >> Hi Experts, > >> > >> I am using GRUB2 on intel apollo lake board. This board does not have IO > >> mapped uart instead it has 8250 memory mapped UART. > > Could you share some details about the board? > > >> GRUB2 does not recognize memory mapped uart and gives error ("serial > port > >> COM0 not found). There is a 8250 memory mapped driver available in > coreboot. > >> Is it possible to port that driver to Grub2? > > My patch set adds support for 8250 MMIO PCI cards. Is the UART on your > board connected via PCI? > > Best, > Matthias. > [-- Attachment #2: Type: text/html, Size: 2048 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 9:51 ` Gailu Singh @ 2017-03-01 9:57 ` Gailu Singh 2017-03-01 10:32 ` Gailu Singh 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-01 9:57 UTC (permalink / raw) To: Matthias Lange; +Cc: Andrei Borzenkov, The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 1432 bytes --] Sorry for typo. I meant 8250 instead of 8050 in last email On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com> wrote: > My board is Intel Oxbohill CRB (Apollo lake). On my board UART are not > connected to PCI. > > I am using grub2 payload loaded by coreboot. UART works fine in coreboot > by using memory mapped 8050 driver (https://github.com/coreboot/ > coreboot/blob/master/src/drivers/uart/uart8250mem.c), however when grub2 > is loaded it refuses to recognize UART. > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange < > matthias.lange@kernkonzept.com> wrote: > >> Hi, >> >> On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: >> > please test patches from Matthias Lange >> > >> > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html >> > >> > >> > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com> wrote: >> >> Hi Experts, >> >> >> >> I am using GRUB2 on intel apollo lake board. This board does not have >> IO >> >> mapped uart instead it has 8250 memory mapped UART. >> >> Could you share some details about the board? >> >> >> GRUB2 does not recognize memory mapped uart and gives error ("serial >> port >> >> COM0 not found). There is a 8250 memory mapped driver available in >> coreboot. >> >> Is it possible to port that driver to Grub2? >> >> My patch set adds support for 8250 MMIO PCI cards. Is the UART on your >> board connected via PCI? >> >> Best, >> Matthias. >> > > [-- Attachment #2: Type: text/html, Size: 2549 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 9:57 ` Gailu Singh @ 2017-03-01 10:32 ` Gailu Singh 2017-03-01 10:57 ` Matthias Lange 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-01 10:32 UTC (permalink / raw) To: Matthias Lange; +Cc: Andrei Borzenkov, The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 2363 bytes --] I checked coreboot where in the memory it is mapped and it seems to be on PCIE. Relevant code from coreboot. So I am hopeful that patch will work. --------- uintptr_t uart_platform_base(int idx) { u8 *pcie; u32 tmp; idx = idx & 3; pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); tmp = read32 (pcie + PCI_BASE_ADDRESS_0); if (tmp == 0xFFFFFFFF) { /* the device might be hidden */ return LPSS_UART_BASE_ADDRESS; } else { return (uintptr_t) (tmp & 0xFFFFFFF0); } } --------- I applied the patches and run make clean followed by make but build failed as follows ------------------------ cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst || (rm -f moddep.lst; exit 1) grub_ns8250_pci_mmio_init in serial is not defined make[3]: *** [moddep.lst] Error 1 ------------------------ On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com> wrote: > Sorry for typo. I meant 8250 instead of 8050 in last email > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com> wrote: > >> My board is Intel Oxbohill CRB (Apollo lake). On my board UART are not >> connected to PCI. >> >> I am using grub2 payload loaded by coreboot. UART works fine in coreboot >> by using memory mapped 8050 driver (https://github.com/coreboot/c >> oreboot/blob/master/src/drivers/uart/uart8250mem.c), however when grub2 >> is loaded it refuses to recognize UART. >> >> >> >> On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange < >> matthias.lange@kernkonzept.com> wrote: >> >>> Hi, >>> >>> On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: >>> > please test patches from Matthias Lange >>> > >>> > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html >>> > >>> > >>> > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com> wrote: >>> >> Hi Experts, >>> >> >>> >> I am using GRUB2 on intel apollo lake board. This board does not have >>> IO >>> >> mapped uart instead it has 8250 memory mapped UART. >>> >>> Could you share some details about the board? >>> >>> >> GRUB2 does not recognize memory mapped uart and gives error ("serial >>> port >>> >> COM0 not found). There is a 8250 memory mapped driver available in >>> coreboot. >>> >> Is it possible to port that driver to Grub2? >>> >>> My patch set adds support for 8250 MMIO PCI cards. Is the UART on your >>> board connected via PCI? >>> >>> Best, >>> Matthias. >>> >> >> > [-- Attachment #2: Type: text/html, Size: 5220 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 10:32 ` Gailu Singh @ 2017-03-01 10:57 ` Matthias Lange 2017-03-01 11:04 ` Gailu Singh 0 siblings, 1 reply; 15+ messages in thread From: Matthias Lange @ 2017-03-01 10:57 UTC (permalink / raw) To: Gailu Singh; +Cc: The development of GNU GRUB On 03/01/2017 11:32 AM, Gailu Singh wrote: > I checked coreboot where in the memory it is mapped and it seems to be > on PCIE. Relevant code from coreboot. So I am hopeful that patch will work. > --------- > uintptr_t uart_platform_base(int idx) > { > u8 *pcie; > u32 tmp; > idx = idx & 3; > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > if (tmp == 0xFFFFFFFF) { > /* the device might be hidden */ > return LPSS_UART_BASE_ADDRESS; > } else { > return (uintptr_t) (tmp & 0xFFFFFFF0); > } > } > --------- This looks promising. Could you extract the PCI vendor and device ID please? My current implementation currently only supports OXSemi chips. > I applied the patches and run make clean followed by make but build > failed as follows > ------------------------ > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst || (rm -f > moddep.lst; exit 1) > grub_ns8250_pci_mmio_init in serial is not defined > make[3]: *** [moddep.lst] Error 1 > ------------------------ Hmmm, grub_ns8250_pci_mmio_init is defined in include/grub/serial.h. Could you check that please? I failed to reproduce your problem, maybe I did something different? (master checked out) /tmp/grub $ /path/to/grub-src/configure --with-platform=efi /tmp/grub $ make -j12 # success (applied my three patches) /tmp/grub $ make clean /tmp/grub $ make -j12 # success Matthias. > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com > <mailto:gailu96@gmail.com>> wrote: > > Sorry for typo. I meant 8250 instead of 8050 in last email > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com > <mailto:gailu96@gmail.com>> wrote: > > My board is Intel Oxbohill CRB (Apollo lake). On my board UART > are not connected to PCI. > > I am using grub2 payload loaded by coreboot. UART works fine in > coreboot by using memory mapped 8050 driver > (https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c > <https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c>), > however when grub2 is loaded it refuses to recognize UART. > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange > <matthias.lange@kernkonzept.com > <mailto:matthias.lange@kernkonzept.com>> wrote: > > Hi, > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > please test patches from Matthias Lange > > > > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html > <https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html> > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh <gailu96@gmail.com <mailto:gailu96@gmail.com>> wrote: > >> Hi Experts, > >> > >> I am using GRUB2 on intel apollo lake board. This board does not have IO > >> mapped uart instead it has 8250 memory mapped UART. > > Could you share some details about the board? > > >> GRUB2 does not recognize memory mapped uart and gives error ("serial port > >> COM0 not found). There is a 8250 memory mapped driver available in coreboot. > >> Is it possible to port that driver to Grub2? > > My patch set adds support for 8250 MMIO PCI cards. Is the > UART on your > board connected via PCI? > > Best, > Matthias. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 10:57 ` Matthias Lange @ 2017-03-01 11:04 ` Gailu Singh 2017-03-03 12:03 ` Gailu Singh 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-01 11:04 UTC (permalink / raw) To: Matthias Lange; +Cc: The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 4646 bytes --] Build problem was due to not running ./configure. I only did make clean and make. Build issue is now resolved after running configure. Only cosmetic change in your patch. ============= static void read_bars(grub_pci_device_t dev, struct grub_serial_board *board) { for (unsigned bar = 0; bar < NUM_BARS; ++bar) changed to ============= static void read_bars(grub_pci_device_t dev, struct grub_serial_board *board) { unsigned bar; for (bar = 0; bar < NUM_BARS; ++bar) ============ I was getting error for C99 enforcement error during build(‘for’ loop initial declarations are only allowed in C99 mode) I will check PCI vendor ID and Device ID and get back to you. On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange < matthias.lange@kernkonzept.com> wrote: > On 03/01/2017 11:32 AM, Gailu Singh wrote: > > I checked coreboot where in the memory it is mapped and it seems to be > > on PCIE. Relevant code from coreboot. So I am hopeful that patch will > work. > > --------- > > uintptr_t uart_platform_base(int idx) > > { > > u8 *pcie; > > u32 tmp; > > idx = idx & 3; > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > if (tmp == 0xFFFFFFFF) { > > /* the device might be hidden */ > > return LPSS_UART_BASE_ADDRESS; > > } else { > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > } > > } > > --------- > > This looks promising. Could you extract the PCI vendor and device ID > please? My current implementation currently only supports OXSemi chips. > > > I applied the patches and run make clean followed by make but build > > failed as follows > > ------------------------ > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst || (rm -f > > moddep.lst; exit 1) > > grub_ns8250_pci_mmio_init in serial is not defined > > make[3]: *** [moddep.lst] Error 1 > > ------------------------ > > Hmmm, grub_ns8250_pci_mmio_init is defined in include/grub/serial.h. > Could you check that please? I failed to reproduce your problem, maybe I > did something different? > > (master checked out) > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi > /tmp/grub $ make -j12 # success > (applied my three patches) > /tmp/grub $ make clean > /tmp/grub $ make -j12 # success > > Matthias. > > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com > > <mailto:gailu96@gmail.com>> wrote: > > > > Sorry for typo. I meant 8250 instead of 8050 in last email > > > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com > > <mailto:gailu96@gmail.com>> wrote: > > > > My board is Intel Oxbohill CRB (Apollo lake). On my board UART > > are not connected to PCI. > > > > I am using grub2 payload loaded by coreboot. UART works fine in > > coreboot by using memory mapped 8050 driver > > (https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c>), > > however when grub2 is loaded it refuses to recognize UART. > > > > > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange > > <matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com>> wrote: > > > > Hi, > > > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > > please test patches from Matthias Lange > > > > > > https://lists.gnu.org/archive/html/grub-devel/2017-02/ > msg00104.html > > <https://lists.gnu.org/archive/html/grub-devel/2017- > 02/msg00104.html> > > > > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh < > gailu96@gmail.com <mailto:gailu96@gmail.com>> wrote: > > >> Hi Experts, > > >> > > >> I am using GRUB2 on intel apollo lake board. This board > does not have IO > > >> mapped uart instead it has 8250 memory mapped UART. > > > > Could you share some details about the board? > > > > >> GRUB2 does not recognize memory mapped uart and gives > error ("serial port > > >> COM0 not found). There is a 8250 memory mapped driver > available in coreboot. > > >> Is it possible to port that driver to Grub2? > > > > My patch set adds support for 8250 MMIO PCI cards. Is the > > UART on your > > board connected via PCI? > > > > Best, > > Matthias. > [-- Attachment #2: Type: text/html, Size: 7070 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-01 11:04 ` Gailu Singh @ 2017-03-03 12:03 ` Gailu Singh 2017-03-03 13:41 ` Matthias Lange 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-03 12:03 UTC (permalink / raw) To: Matthias Lange; +Cc: The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 8898 bytes --] Sorry it took some time to boot board with Linux. Not sure how to determine correct Device ID, Vendor ID seems to be all 8086 on the oard My lspci -nn command output is root@localhost:~# lspci -nn 00:00.0 Host bridge [0600]: Intel Corporation Device [8086:5af0] (rev 0b) 00:00.1 Signal processing controller [1180]: Intel Corporation Device [8086:5a8c] (rev 0b) 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:5a84] (rev 0b) 00:0e.0 Audio device [0403]: Intel Corporation Device [8086:5a98] (rev 0b) 00:0f.0 Communication controller [0780]: Intel Corporation Device [8086:5a9a] (rev 0b) 00:11.0 Unclassified device [0050]: Intel Corporation Device [8086:5aa2] (rev 0b) 00:12.0 SATA controller [0106]: Intel Corporation Device [8086:5ae3] (rev 0b) 00:13.0 PCI bridge [0604]: Intel Corporation Device [8086:5ad8] (rev fb) 00:13.2 PCI bridge [0604]: Intel Corporation Device [8086:5ada] (rev fb) 00:13.3 PCI bridge [0604]: Intel Corporation Device [8086:5adb] (rev fb) 00:14.0 PCI bridge [0604]: Intel Corporation Device [8086:5ad6] (rev fb) 00:14.1 PCI bridge [0604]: Intel Corporation Device [8086:5ad7] (rev fb) 00:15.0 USB controller [0c03]: Intel Corporation Device [8086:5aa8] (rev 0b) 00:15.1 USB controller [0c03]: Intel Corporation Device [8086:5aaa] (rev 0b) 00:16.0 Signal processing controller [1180]: Intel Corporation Device [8086:5aac] (rev 0b) 00:16.1 Signal processing controller [1180]: Intel Corporation Device [8086:5aae] (rev 0b) 00:16.2 Signal processing controller [1180]: Intel Corporation Device [8086:5ab0] (rev 0b) 00:16.3 Signal processing controller [1180]: Intel Corporation Device [8086:5ab2] (rev 0b) 00:17.0 Signal processing controller [1180]: Intel Corporation Device [8086:5ab4] (rev 0b) 00:17.1 Signal processing controller [1180]: Intel Corporation Device [8086:5ab6] (rev 0b) 00:17.2 Signal processing controller [1180]: Intel Corporation Device [8086:5ab8] (rev 0b) 00:17.3 Signal processing controller [1180]: Intel Corporation Device [8086:5aba] (rev 0b) 00:18.0 Signal processing controller [1180]: Intel Corporation Device [8086:5abc] (rev 0b) 00:18.1 Signal processing controller [1180]: Intel Corporation Device [8086:5abe] (rev 0b) 00:18.2 Signal processing controller [1180]: Intel Corporation Device [8086:5ac0] (rev 0b) 00:18.3 Signal processing controller [1180]: Intel Corporation Device [8086:5aee] (rev 0b) 00:19.0 Signal processing controller [1180]: Intel Corporation Device [8086:5ac2] (rev 0b) 00:19.1 Signal processing controller [1180]: Intel Corporation Device [8086:5ac4] (rev 0b) 00:19.2 Signal processing controller [1180]: Intel Corporation Device [8086:5ac6] (rev 0b) 00:1b.0 SD Host controller [0805]: Intel Corporation Device [8086:5aca] (rev 0b) 00:1c.0 SD Host controller [0805]: Intel Corporation Device [8086:5acc] (rev 0b) 00:1e.0 SD Host controller [0805]: Intel Corporation Device [8086:5ad0] (rev 0b) 00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:5ae8] (rev 0b) 00:1f.1 SMBus [0c05]: Intel Corporation Device [8086:5ad4] (rev 0b) 02:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:157b] (rev 03) root@localhost:~# In coreboot it initializes as uintptr_t uart_platform_base(int idx) { u8 *pcie; u32 tmp; idx = idx & 3; pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); tmp = read32 (pcie + PCI_BASE_ADDRESS_0); if (tmp == 0xFFFFFFFF) { /* the device might be hidden */ return LPSS_UART_BASE_ADDRESS; } else { return (uintptr_t) (tmp & 0xFFFFFFF0); } } #define PCIE_MMIO(Bus, Device, Function, Register ) \ ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \ (UINTN)(Bus << 20) + \ (UINTN)(Device << 15) + \ (UINTN)(Function << 12) + \ (UINTN)(Register) \ ) #define PCH_DEV_SLOT_UART 0x18 There are 4 uarts (idx 0 to 3) Is above information sufficient to find the required information? On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gailu96@gmail.com> wrote: > Build problem was due to not running ./configure. I only did make clean > and make. Build issue is now resolved after running configure. Only > cosmetic change in your patch. > > ============= > static void > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > { > for (unsigned bar = 0; bar < NUM_BARS; ++bar) > > changed to > ============= > static void > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > { > unsigned bar; > > for (bar = 0; bar < NUM_BARS; ++bar) > ============ > > I was getting error for C99 enforcement error during build(‘for’ loop > initial declarations are only allowed in C99 mode) > > > I will check PCI vendor ID and Device ID and get back to you. > > > > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange < > matthias.lange@kernkonzept.com> wrote: > >> On 03/01/2017 11:32 AM, Gailu Singh wrote: >> > I checked coreboot where in the memory it is mapped and it seems to be >> > on PCIE. Relevant code from coreboot. So I am hopeful that patch will >> work. >> > --------- >> > uintptr_t uart_platform_base(int idx) >> > { >> > u8 *pcie; >> > u32 tmp; >> > idx = idx & 3; >> > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); >> > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); >> > if (tmp == 0xFFFFFFFF) { >> > /* the device might be hidden */ >> > return LPSS_UART_BASE_ADDRESS; >> > } else { >> > return (uintptr_t) (tmp & 0xFFFFFFF0); >> > } >> > } >> > --------- >> >> This looks promising. Could you extract the PCI vendor and device ID >> please? My current implementation currently only supports OXSemi chips. >> >> > I applied the patches and run make clean followed by make but build >> > failed as follows >> > ------------------------ >> > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst || (rm -f >> > moddep.lst; exit 1) >> > grub_ns8250_pci_mmio_init in serial is not defined >> > make[3]: *** [moddep.lst] Error 1 >> > ------------------------ >> >> Hmmm, grub_ns8250_pci_mmio_init is defined in include/grub/serial.h. >> Could you check that please? I failed to reproduce your problem, maybe I >> did something different? >> >> (master checked out) >> /tmp/grub $ /path/to/grub-src/configure --with-platform=efi >> /tmp/grub $ make -j12 # success >> (applied my three patches) >> /tmp/grub $ make clean >> /tmp/grub $ make -j12 # success >> >> Matthias. >> >> > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com >> > <mailto:gailu96@gmail.com>> wrote: >> > >> > Sorry for typo. I meant 8250 instead of 8050 in last email >> > >> > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com >> > <mailto:gailu96@gmail.com>> wrote: >> > >> > My board is Intel Oxbohill CRB (Apollo lake). On my board UART >> > are not connected to PCI. >> > >> > I am using grub2 payload loaded by coreboot. UART works fine in >> > coreboot by using memory mapped 8050 driver >> > (https://github.com/coreboot/coreboot/blob/master/src/drive >> rs/uart/uart8250mem.c >> > <https://github.com/coreboot/coreboot/blob/master/src/drive >> rs/uart/uart8250mem.c>), >> > however when grub2 is loaded it refuses to recognize UART. >> > >> > >> > >> > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange >> > <matthias.lange@kernkonzept.com >> > <mailto:matthias.lange@kernkonzept.com>> wrote: >> > >> > Hi, >> > >> > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: >> > > please test patches from Matthias Lange >> > > >> > > https://lists.gnu.org/archive/ >> html/grub-devel/2017-02/msg00104.html >> > <https://lists.gnu.org/archive/html/grub-devel/2017-02/ >> msg00104.html> >> > > >> > > >> > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh < >> gailu96@gmail.com <mailto:gailu96@gmail.com>> wrote: >> > >> Hi Experts, >> > >> >> > >> I am using GRUB2 on intel apollo lake board. This board >> does not have IO >> > >> mapped uart instead it has 8250 memory mapped UART. >> > >> > Could you share some details about the board? >> > >> > >> GRUB2 does not recognize memory mapped uart and gives >> error ("serial port >> > >> COM0 not found). There is a 8250 memory mapped driver >> available in coreboot. >> > >> Is it possible to port that driver to Grub2? >> > >> > My patch set adds support for 8250 MMIO PCI cards. Is the >> > UART on your >> > board connected via PCI? >> > >> > Best, >> > Matthias. >> > > [-- Attachment #2: Type: text/html, Size: 13635 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-03 12:03 ` Gailu Singh @ 2017-03-03 13:41 ` Matthias Lange 2017-03-03 14:07 ` Gailu Singh 2017-03-24 17:29 ` Gailu Singh 0 siblings, 2 replies; 15+ messages in thread From: Matthias Lange @ 2017-03-03 13:41 UTC (permalink / raw) To: Gailu Singh; +Cc: The development of GNU GRUB Hi, On 03/03/2017 01:03 PM, Gailu Singh wrote: > Sorry it took some time to boot board with Linux. Not sure how to > determine correct Device ID, Vendor ID seems to be all 8086 on the oard > My lspci -nn command output is > > root@localhost:~# lspci -nn [...] > 00:18.0 Signal processing controller [1180]: Intel Corporation Device > [8086:5abc] (rev 0b) > 00:18.1 Signal processing controller [1180]: Intel Corporation Device > [8086:5abe] (rev 0b) > 00:18.2 Signal processing controller [1180]: Intel Corporation Device > [8086:5ac0] (rev 0b) > 00:18.3 Signal processing controller [1180]: Intel Corporation Device > [8086:5aee] (rev 0b) These four devices are the HSUARTs (high speed UART). According to the documentation they are 16550A compatible UARTs. [...] The patches I send to the mailing list do not support the Intel UARTs right now, because they only match for OXSemi IDs. One has to add a similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. First I need to have a look into the Linux driver to get more insights. If I am lucky we also might have a board with an Intel Quark SoC flying around in the office. Best, Matthias. > > In coreboot it initializes as > > uintptr_t uart_platform_base(int idx) > { > u8 *pcie; > u32 tmp; > idx = idx & 3; > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > if (tmp == 0xFFFFFFFF) { > /* the device might be hidden */ > return LPSS_UART_BASE_ADDRESS; > } else { > return (uintptr_t) (tmp & 0xFFFFFFF0); > } > } > > #define PCIE_MMIO(Bus, Device, Function, Register ) \ > ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \ > (UINTN)(Bus << 20) + \ > (UINTN)(Device << 15) + \ > (UINTN)(Function << 12) + \ > (UINTN)(Register) \ > ) > > > #define PCH_DEV_SLOT_UART0x18 > > There are 4 uarts (idx 0 to 3) > > Is above information sufficient to find the required information? > > On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gailu96@gmail.com > <mailto:gailu96@gmail.com>> wrote: > > Build problem was due to not running ./configure. I only did make > clean and make. Build issue is now resolved after running > configure. Only cosmetic change in your patch. > > ============= > static void > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > { > for (unsigned bar = 0; bar < NUM_BARS; ++bar) > > changed to > ============= > static void > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > { > unsigned bar; > > for (bar = 0; bar < NUM_BARS; ++bar) > ============ > > I was getting error for C99 enforcement error during build(‘for’ > loop initial declarations are only allowed in C99 mode) > > > I will check PCI vendor ID and Device ID and get back to you. > > > > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange > <matthias.lange@kernkonzept.com > <mailto:matthias.lange@kernkonzept.com>> wrote: > > On 03/01/2017 11:32 AM, Gailu Singh wrote: > > I checked coreboot where in the memory it is mapped and it seems to be > > on PCIE. Relevant code from coreboot. So I am hopeful that patch will work. > > --------- > > uintptr_t uart_platform_base(int idx) > > { > > u8 *pcie; > > u32 tmp; > > idx = idx & 3; > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > if (tmp == 0xFFFFFFFF) { > > /* the device might be hidden */ > > return LPSS_UART_BASE_ADDRESS; > > } else { > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > } > > } > > --------- > > This looks promising. Could you extract the PCI vendor and device ID > please? My current implementation currently only supports OXSemi > chips. > > > I applied the patches and run make clean followed by make but build > > failed as follows > > ------------------------ > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst || (rm -f > > moddep.lst; exit 1) > > grub_ns8250_pci_mmio_init in serial is not defined > > make[3]: *** [moddep.lst] Error 1 > > ------------------------ > > Hmmm, grub_ns8250_pci_mmio_init is defined in include/grub/serial.h. > Could you check that please? I failed to reproduce your problem, > maybe I > did something different? > > (master checked out) > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi > /tmp/grub $ make -j12 # success > (applied my three patches) > /tmp/grub $ make clean > /tmp/grub $ make -j12 # success > > Matthias. > > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com <mailto:gailu96@gmail.com> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > > Sorry for typo. I meant 8250 instead of 8050 in last email > > > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh <gailu96@gmail.com <mailto:gailu96@gmail.com> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > > My board is Intel Oxbohill CRB (Apollo lake). On my board UART > > are not connected to PCI. > > > > I am using grub2 payload loaded by coreboot. UART works fine in > > coreboot by using memory mapped 8050 driver > > (https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c > <https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c> > > > <https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c > <https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c>>), > > however when grub2 is loaded it refuses to recognize UART. > > > > > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange > > <matthias.lange@kernkonzept.com > <mailto:matthias.lange@kernkonzept.com> > > <mailto:matthias.lange@kernkonzept.com > <mailto:matthias.lange@kernkonzept.com>>> wrote: > > > > Hi, > > > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > > please test patches from Matthias Lange > > > > > > https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html > <https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html> > > <https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html > <https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html>> > > > > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh > <gailu96@gmail.com <mailto:gailu96@gmail.com> > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > >> Hi Experts, > > >> > > >> I am using GRUB2 on intel apollo lake board. > This board does not have IO > > >> mapped uart instead it has 8250 memory mapped UART. > > > > Could you share some details about the board? > > > > >> GRUB2 does not recognize memory mapped uart and > gives error ("serial port > > >> COM0 not found). There is a 8250 memory mapped > driver available in coreboot. > > >> Is it possible to port that driver to Grub2? > > > > My patch set adds support for 8250 MMIO PCI cards. > Is the > > UART on your > > board connected via PCI? > > > > Best, > > Matthias. -- Matthias Lange, matthias.lange@kernkonzept.com, +49-351-41 888 614 Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. Geschäftsführer: Dr.-Ing. Michael Hohmuth ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-03 13:41 ` Matthias Lange @ 2017-03-03 14:07 ` Gailu Singh 2017-03-24 17:29 ` Gailu Singh 1 sibling, 0 replies; 15+ messages in thread From: Gailu Singh @ 2017-03-03 14:07 UTC (permalink / raw) To: Matthias Lange; +Cc: The development of GNU GRUB [-- Attachment #1.1: Type: text/plain, Size: 9781 bytes --] If this help finding linux driver, I am attaching my full linux kernel cofiguration. In kernel config, I guess driver is enabled with # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_FINTEK is not set # CONFIG_SERIAL_8250_MID is not set I get the linux console on ttyS2 (console=ttyS2,115200) On Fri, Mar 3, 2017 at 7:11 PM, Matthias Lange < matthias.lange@kernkonzept.com> wrote: > Hi, > > On 03/03/2017 01:03 PM, Gailu Singh wrote: > > Sorry it took some time to boot board with Linux. Not sure how to > > determine correct Device ID, Vendor ID seems to be all 8086 on the oard > > My lspci -nn command output is > > > > root@localhost:~# lspci -nn > > [...] > > > 00:18.0 Signal processing controller [1180]: Intel Corporation Device > > [8086:5abc] (rev 0b) > > 00:18.1 Signal processing controller [1180]: Intel Corporation Device > > [8086:5abe] (rev 0b) > > 00:18.2 Signal processing controller [1180]: Intel Corporation Device > > [8086:5ac0] (rev 0b) > > 00:18.3 Signal processing controller [1180]: Intel Corporation Device > > [8086:5aee] (rev 0b) > > These four devices are the HSUARTs (high speed UART). According to the > documentation they are 16550A compatible UARTs. > > [...] > > The patches I send to the mailing list do not support the Intel UARTs > right now, because they only match for OXSemi IDs. One has to add a > similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. > > First I need to have a look into the Linux driver to get more insights. > If I am lucky we also might have a board with an Intel Quark SoC flying > around in the office. > > Best, > Matthias. > > > > > In coreboot it initializes as > > > > uintptr_t uart_platform_base(int idx) > > { > > u8 *pcie; > > u32 tmp; > > idx = idx & 3; > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > if (tmp == 0xFFFFFFFF) { > > /* the device might be hidden */ > > return LPSS_UART_BASE_ADDRESS; > > } else { > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > } > > } > > > > #define PCIE_MMIO(Bus, Device, Function, Register ) \ > > ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \ > > (UINTN)(Bus << 20) + \ > > (UINTN)(Device << 15) + \ > > (UINTN)(Function << 12) + \ > > (UINTN)(Register) \ > > ) > > > > > > #define PCH_DEV_SLOT_UART0x18 > > > > There are 4 uarts (idx 0 to 3) > > > > Is above information sufficient to find the required information? > > > > On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gailu96@gmail.com > > <mailto:gailu96@gmail.com>> wrote: > > > > Build problem was due to not running ./configure. I only did make > > clean and make. Build issue is now resolved after running > > configure. Only cosmetic change in your patch. > > > > ============= > > static void > > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > > { > > for (unsigned bar = 0; bar < NUM_BARS; ++bar) > > > > changed to > > ============= > > static void > > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > > { > > unsigned bar; > > > > for (bar = 0; bar < NUM_BARS; ++bar) > > ============ > > > > I was getting error for C99 enforcement error during build(‘for’ > > loop initial declarations are only allowed in C99 mode) > > > > > > I will check PCI vendor ID and Device ID and get back to you. > > > > > > > > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange > > <matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com>> wrote: > > > > On 03/01/2017 11:32 AM, Gailu Singh wrote: > > > I checked coreboot where in the memory it is mapped and it > seems to be > > > on PCIE. Relevant code from coreboot. So I am hopeful that > patch will work. > > > --------- > > > uintptr_t uart_platform_base(int idx) > > > { > > > u8 *pcie; > > > u32 tmp; > > > idx = idx & 3; > > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > > if (tmp == 0xFFFFFFFF) { > > > /* the device might be hidden */ > > > return LPSS_UART_BASE_ADDRESS; > > > } else { > > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > > } > > > } > > > --------- > > > > This looks promising. Could you extract the PCI vendor and > device ID > > please? My current implementation currently only supports OXSemi > > chips. > > > > > I applied the patches and run make clean followed by make but > build > > > failed as follows > > > ------------------------ > > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst > || (rm -f > > > moddep.lst; exit 1) > > > grub_ns8250_pci_mmio_init in serial is not defined > > > make[3]: *** [moddep.lst] Error 1 > > > ------------------------ > > > > Hmmm, grub_ns8250_pci_mmio_init is defined in > include/grub/serial.h. > > Could you check that please? I failed to reproduce your problem, > > maybe I > > did something different? > > > > (master checked out) > > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi > > /tmp/grub $ make -j12 # success > > (applied my three patches) > > /tmp/grub $ make clean > > /tmp/grub $ make -j12 # success > > > > Matthias. > > > > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com > <mailto:gailu96@gmail.com> > > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > > > > Sorry for typo. I meant 8250 instead of 8050 in last email > > > > > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh < > gailu96@gmail.com <mailto:gailu96@gmail.com> > > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> > wrote: > > > > > > My board is Intel Oxbohill CRB (Apollo lake). On my > board UART > > > are not connected to PCI. > > > > > > I am using grub2 payload loaded by coreboot. UART > works fine in > > > coreboot by using memory mapped 8050 driver > > > (https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c> > > > > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c>>), > > > however when grub2 is loaded it refuses to recognize > UART. > > > > > > > > > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange > > > <matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com> > > > <mailto:matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com>>> wrote: > > > > > > Hi, > > > > > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > > > please test patches from Matthias Lange > > > > > > > > https://lists.gnu.org/archive/ > html/grub-devel/2017-02/msg00104.html > > <https://lists.gnu.org/archive/html/grub-devel/2017- > 02/msg00104.html> > > > <https://lists.gnu.org/ > archive/html/grub-devel/2017-02/msg00104.html > > <https://lists.gnu.org/archive/html/grub-devel/2017- > 02/msg00104.html>> > > > > > > > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh > > <gailu96@gmail.com <mailto:gailu96@gmail.com> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > >> Hi Experts, > > > >> > > > >> I am using GRUB2 on intel apollo lake board. > > This board does not have IO > > > >> mapped uart instead it has 8250 memory mapped > UART. > > > > > > Could you share some details about the board? > > > > > > >> GRUB2 does not recognize memory mapped uart and > > gives error ("serial port > > > >> COM0 not found). There is a 8250 memory mapped > > driver available in coreboot. > > > >> Is it possible to port that driver to Grub2? > > > > > > My patch set adds support for 8250 MMIO PCI cards. > > Is the > > > UART on your > > > board connected via PCI? > > > > > > Best, > > > Matthias. > > > -- > Matthias Lange, matthias.lange@kernkonzept.com, +49-351-41 888 614 > > Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. > Geschäftsführer: Dr.-Ing. Michael Hohmuth > > [-- Attachment #1.2: Type: text/html, Size: 14894 bytes --] [-- Attachment #2: .config --] [-- Type: application/xml, Size: 108345 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-03 13:41 ` Matthias Lange 2017-03-03 14:07 ` Gailu Singh @ 2017-03-24 17:29 ` Gailu Singh 2017-03-27 17:59 ` Gailu Singh 1 sibling, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-24 17:29 UTC (permalink / raw) To: Matthias Lange; +Cc: The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 11195 bytes --] Hi Matthias, The patches I send to the mailing list do not support the Intel UARTs right now, because they only match for OXSemi IDs. One has to add a similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. I have changed the ns8250_pci_mmio_iter and enabled two debug print in ns8250-pci-mmio.c and I see following prints. Found Intel PCI UART bar=c2539004 (MEM, sz=4) bar=c2539004 (MEM, sz=4) in my grub.cfg I have serial --port=pci:0:0 --speed=115200 terminal_input --append serial_pci:0:0 terminal_output --append serial_pci:0:0 But I do not see any output on my serial console. I changed board.base_baud from 4000000 to 115200. Any other debug print that I could enable to proceed further on this? My changed code ----------------------------------- static int ns8250_pci_mmio_iter(grub_pci_device_t dev, grub_pci_id_t pciid, void *data) { unsigned vendor, device; struct drv_data *d = (struct drv_data *)data; if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM) return 0; vendor = pciid & 0xffff; device = pciid >> 16; if (vendor == 0x8086 && device == 0x5ac0) { struct grub_serial_port *port = &ports[d->num_ports]; struct grub_serial_board *b = &ports[d->num_ports].board; if (1) grub_printf("Found Intel PCI UART\n"); read_bars(dev, b); port->board.num_ports = 1; port->board.base_baud = 115200; port->board.port_offset = 0x200; port->board.base_offset = 0x1000; port->pcidev.bus = dev.bus; port->pcidev.device = dev.device; port->pcidev.function = dev.function; port->port_num = 0; port->card = d->cards; port->mmio_base = port->board.bars[0].base + port->board.base_offset + port->port_num * port->board.port_offset; d->num_ports += 1; if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM) return 0; enable_mmio (dev); d->cards += 1; } return 0; } ----------------- On Fri, Mar 3, 2017 at 7:11 PM, Matthias Lange < matthias.lange@kernkonzept.com> wrote: > Hi, > > On 03/03/2017 01:03 PM, Gailu Singh wrote: > > Sorry it took some time to boot board with Linux. Not sure how to > > determine correct Device ID, Vendor ID seems to be all 8086 on the oard > > My lspci -nn command output is > > > > root@localhost:~# lspci -nn > > [...] > > > 00:18.0 Signal processing controller [1180]: Intel Corporation Device > > [8086:5abc] (rev 0b) > > 00:18.1 Signal processing controller [1180]: Intel Corporation Device > > [8086:5abe] (rev 0b) > > 00:18.2 Signal processing controller [1180]: Intel Corporation Device > > [8086:5ac0] (rev 0b) > > 00:18.3 Signal processing controller [1180]: Intel Corporation Device > > [8086:5aee] (rev 0b) > > These four devices are the HSUARTs (high speed UART). According to the > documentation they are 16550A compatible UARTs. > > [...] > > The patches I send to the mailing list do not support the Intel UARTs > right now, because they only match for OXSemi IDs. One has to add a > similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. > > First I need to have a look into the Linux driver to get more insights. > If I am lucky we also might have a board with an Intel Quark SoC flying > around in the office. > > Best, > Matthias. > > > > > In coreboot it initializes as > > > > uintptr_t uart_platform_base(int idx) > > { > > u8 *pcie; > > u32 tmp; > > idx = idx & 3; > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > if (tmp == 0xFFFFFFFF) { > > /* the device might be hidden */ > > return LPSS_UART_BASE_ADDRESS; > > } else { > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > } > > } > > > > #define PCIE_MMIO(Bus, Device, Function, Register ) \ > > ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \ > > (UINTN)(Bus << 20) + \ > > (UINTN)(Device << 15) + \ > > (UINTN)(Function << 12) + \ > > (UINTN)(Register) \ > > ) > > > > > > #define PCH_DEV_SLOT_UART0x18 > > > > There are 4 uarts (idx 0 to 3) > > > > Is above information sufficient to find the required information? > > > > On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gailu96@gmail.com > > <mailto:gailu96@gmail.com>> wrote: > > > > Build problem was due to not running ./configure. I only did make > > clean and make. Build issue is now resolved after running > > configure. Only cosmetic change in your patch. > > > > ============= > > static void > > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > > { > > for (unsigned bar = 0; bar < NUM_BARS; ++bar) > > > > changed to > > ============= > > static void > > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) > > { > > unsigned bar; > > > > for (bar = 0; bar < NUM_BARS; ++bar) > > ============ > > > > I was getting error for C99 enforcement error during build(‘for’ > > loop initial declarations are only allowed in C99 mode) > > > > > > I will check PCI vendor ID and Device ID and get back to you. > > > > > > > > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange > > <matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com>> wrote: > > > > On 03/01/2017 11:32 AM, Gailu Singh wrote: > > > I checked coreboot where in the memory it is mapped and it > seems to be > > > on PCIE. Relevant code from coreboot. So I am hopeful that > patch will work. > > > --------- > > > uintptr_t uart_platform_base(int idx) > > > { > > > u8 *pcie; > > > u32 tmp; > > > idx = idx & 3; > > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); > > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); > > > if (tmp == 0xFFFFFFFF) { > > > /* the device might be hidden */ > > > return LPSS_UART_BASE_ADDRESS; > > > } else { > > > return (uintptr_t) (tmp & 0xFFFFFFF0); > > > } > > > } > > > --------- > > > > This looks promising. Could you extract the PCI vendor and > device ID > > please? My current implementation currently only supports OXSemi > > chips. > > > > > I applied the patches and run make clean followed by make but > build > > > failed as follows > > > ------------------------ > > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst > || (rm -f > > > moddep.lst; exit 1) > > > grub_ns8250_pci_mmio_init in serial is not defined > > > make[3]: *** [moddep.lst] Error 1 > > > ------------------------ > > > > Hmmm, grub_ns8250_pci_mmio_init is defined in > include/grub/serial.h. > > Could you check that please? I failed to reproduce your problem, > > maybe I > > did something different? > > > > (master checked out) > > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi > > /tmp/grub $ make -j12 # success > > (applied my three patches) > > /tmp/grub $ make clean > > /tmp/grub $ make -j12 # success > > > > Matthias. > > > > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh <gailu96@gmail.com > <mailto:gailu96@gmail.com> > > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > > > > Sorry for typo. I meant 8250 instead of 8050 in last email > > > > > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh < > gailu96@gmail.com <mailto:gailu96@gmail.com> > > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> > wrote: > > > > > > My board is Intel Oxbohill CRB (Apollo lake). On my > board UART > > > are not connected to PCI. > > > > > > I am using grub2 payload loaded by coreboot. UART > works fine in > > > coreboot by using memory mapped 8050 driver > > > (https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c> > > > > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c > > <https://github.com/coreboot/coreboot/blob/master/src/ > drivers/uart/uart8250mem.c>>), > > > however when grub2 is loaded it refuses to recognize > UART. > > > > > > > > > > > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange > > > <matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com> > > > <mailto:matthias.lange@kernkonzept.com > > <mailto:matthias.lange@kernkonzept.com>>> wrote: > > > > > > Hi, > > > > > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: > > > > please test patches from Matthias Lange > > > > > > > > https://lists.gnu.org/archive/ > html/grub-devel/2017-02/msg00104.html > > <https://lists.gnu.org/archive/html/grub-devel/2017- > 02/msg00104.html> > > > <https://lists.gnu.org/ > archive/html/grub-devel/2017-02/msg00104.html > > <https://lists.gnu.org/archive/html/grub-devel/2017- > 02/msg00104.html>> > > > > > > > > > > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh > > <gailu96@gmail.com <mailto:gailu96@gmail.com> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: > > > >> Hi Experts, > > > >> > > > >> I am using GRUB2 on intel apollo lake board. > > This board does not have IO > > > >> mapped uart instead it has 8250 memory mapped > UART. > > > > > > Could you share some details about the board? > > > > > > >> GRUB2 does not recognize memory mapped uart and > > gives error ("serial port > > > >> COM0 not found). There is a 8250 memory mapped > > driver available in coreboot. > > > >> Is it possible to port that driver to Grub2? > > > > > > My patch set adds support for 8250 MMIO PCI cards. > > Is the > > > UART on your > > > board connected via PCI? > > > > > > Best, > > > Matthias. > > > -- > Matthias Lange, matthias.lange@kernkonzept.com, +49-351-41 888 614 > > Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. > Geschäftsführer: Dr.-Ing. Michael Hohmuth > > [-- Attachment #2: Type: text/html, Size: 19789 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-24 17:29 ` Gailu Singh @ 2017-03-27 17:59 ` Gailu Singh 2017-03-27 18:31 ` Lennart Sorensen 0 siblings, 1 reply; 15+ messages in thread From: Gailu Singh @ 2017-03-27 17:59 UTC (permalink / raw) To: Matthias Lange; +Cc: The development of GNU GRUB [-- Attachment #1: Type: text/plain, Size: 11946 bytes --] Hi Matthias, Can you please let me know how following three values are calculated in your patch. I am trying to understand how do I change it for my board. port->board.base_baud = 4000000; port->board.port_offset = 0x200; port->board.base_offset = 0x1000; On Fri, Mar 24, 2017 at 10:59 PM, Gailu Singh <gailu96@gmail.com> wrote: > Hi Matthias, > > The patches I send to the mailing list do not support the Intel UARTs > right now, because they only match for OXSemi IDs. One has to add a > similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. > > I have changed the ns8250_pci_mmio_iter and enabled two debug print in > ns8250-pci-mmio.c and I see following prints. > > Found Intel PCI UART > > bar=c2539004 (MEM, sz=4) > bar=c2539004 (MEM, sz=4) > > in my grub.cfg I have > > serial --port=pci:0:0 --speed=115200 > terminal_input --append serial_pci:0:0 > terminal_output --append serial_pci:0:0 > > But I do not see any output on my serial console. I changed board.base_baud > from 4000000 to 115200. Any other debug print that I could enable to > proceed further on this? > > My changed code > ----------------------------------- > static int > ns8250_pci_mmio_iter(grub_pci_device_t dev, grub_pci_id_t pciid, void > *data) > { > unsigned vendor, device; > struct drv_data *d = (struct drv_data *)data; > > if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM) > return 0; > > vendor = pciid & 0xffff; > device = pciid >> 16; > > if (vendor == 0x8086 && device == 0x5ac0) > { > struct grub_serial_port *port = &ports[d->num_ports]; > struct grub_serial_board *b = &ports[d->num_ports].board; > > if (1) > grub_printf("Found Intel PCI UART\n"); > > read_bars(dev, b); > > port->board.num_ports = 1; > port->board.base_baud = 115200; > port->board.port_offset = 0x200; > port->board.base_offset = 0x1000; > > port->pcidev.bus = dev.bus; > port->pcidev.device = dev.device; > port->pcidev.function = dev.function; > port->port_num = 0; > port->card = d->cards; > port->mmio_base = port->board.bars[0].base + port->board.base_offset > + > port->port_num * port->board.port_offset; > d->num_ports += 1; > > if (d->num_ports >= GRUB_SERIAL_PCI_PORT_NUM) > return 0; > > enable_mmio (dev); > d->cards += 1; > } > > return 0; > } > ----------------- > > > On Fri, Mar 3, 2017 at 7:11 PM, Matthias Lange < > matthias.lange@kernkonzept.com> wrote: > >> Hi, >> >> On 03/03/2017 01:03 PM, Gailu Singh wrote: >> > Sorry it took some time to boot board with Linux. Not sure how to >> > determine correct Device ID, Vendor ID seems to be all 8086 on the oard >> > My lspci -nn command output is >> > >> > root@localhost:~# lspci -nn >> >> [...] >> >> > 00:18.0 Signal processing controller [1180]: Intel Corporation Device >> > [8086:5abc] (rev 0b) >> > 00:18.1 Signal processing controller [1180]: Intel Corporation Device >> > [8086:5abe] (rev 0b) >> > 00:18.2 Signal processing controller [1180]: Intel Corporation Device >> > [8086:5ac0] (rev 0b) >> > 00:18.3 Signal processing controller [1180]: Intel Corporation Device >> > [8086:5aee] (rev 0b) >> >> These four devices are the HSUARTs (high speed UART). According to the >> documentation they are 16550A compatible UARTs. >> >> [...] >> >> The patches I send to the mailing list do not support the Intel UARTs >> right now, because they only match for OXSemi IDs. One has to add a >> similar matching block to 'ns8250_pci_mmio_iter' for the Intel UARTs. >> >> First I need to have a look into the Linux driver to get more insights. >> If I am lucky we also might have a board with an Intel Quark SoC flying >> around in the office. >> >> Best, >> Matthias. >> >> > >> > In coreboot it initializes as >> > >> > uintptr_t uart_platform_base(int idx) >> > { >> > u8 *pcie; >> > u32 tmp; >> > idx = idx & 3; >> > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); >> > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); >> > if (tmp == 0xFFFFFFFF) { >> > /* the device might be hidden */ >> > return LPSS_UART_BASE_ADDRESS; >> > } else { >> > return (uintptr_t) (tmp & 0xFFFFFFF0); >> > } >> > } >> > >> > #define PCIE_MMIO(Bus, Device, Function, Register ) \ >> > ( (UINTN)CONFIG_MMCONF_BASE_ADDRESS + \ >> > (UINTN)(Bus << 20) + \ >> > (UINTN)(Device << 15) + \ >> > (UINTN)(Function << 12) + \ >> > (UINTN)(Register) \ >> > ) >> > >> > >> > #define PCH_DEV_SLOT_UART0x18 >> > >> > There are 4 uarts (idx 0 to 3) >> > >> > Is above information sufficient to find the required information? >> > >> > On Wed, Mar 1, 2017 at 4:34 PM, Gailu Singh <gailu96@gmail.com >> > <mailto:gailu96@gmail.com>> wrote: >> > >> > Build problem was due to not running ./configure. I only did make >> > clean and make. Build issue is now resolved after running >> > configure. Only cosmetic change in your patch. >> > >> > ============= >> > static void >> > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) >> > { >> > for (unsigned bar = 0; bar < NUM_BARS; ++bar) >> > >> > changed to >> > ============= >> > static void >> > read_bars(grub_pci_device_t dev, struct grub_serial_board *board) >> > { >> > unsigned bar; >> > >> > for (bar = 0; bar < NUM_BARS; ++bar) >> > ============ >> > >> > I was getting error for C99 enforcement error during build(‘for’ >> > loop initial declarations are only allowed in C99 mode) >> > >> > >> > I will check PCI vendor ID and Device ID and get back to you. >> > >> > >> > >> > On Wed, Mar 1, 2017 at 4:27 PM, Matthias Lange >> > <matthias.lange@kernkonzept.com >> > <mailto:matthias.lange@kernkonzept.com>> wrote: >> > >> > On 03/01/2017 11:32 AM, Gailu Singh wrote: >> > > I checked coreboot where in the memory it is mapped and it >> seems to be >> > > on PCIE. Relevant code from coreboot. So I am hopeful that >> patch will work. >> > > --------- >> > > uintptr_t uart_platform_base(int idx) >> > > { >> > > u8 *pcie; >> > > u32 tmp; >> > > idx = idx & 3; >> > > pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0); >> > > tmp = read32 (pcie + PCI_BASE_ADDRESS_0); >> > > if (tmp == 0xFFFFFFFF) { >> > > /* the device might be hidden */ >> > > return LPSS_UART_BASE_ADDRESS; >> > > } else { >> > > return (uintptr_t) (tmp & 0xFFFFFFF0); >> > > } >> > > } >> > > --------- >> > >> > This looks promising. Could you extract the PCI vendor and >> device ID >> > please? My current implementation currently only supports OXSemi >> > chips. >> > >> > > I applied the patches and run make clean followed by make >> but build >> > > failed as follows >> > > ------------------------ >> > > cat syminfo.lst | sort | gawk -f ./genmoddep.awk > moddep.lst >> || (rm -f >> > > moddep.lst; exit 1) >> > > grub_ns8250_pci_mmio_init in serial is not defined >> > > make[3]: *** [moddep.lst] Error 1 >> > > ------------------------ >> > >> > Hmmm, grub_ns8250_pci_mmio_init is defined in >> include/grub/serial.h. >> > Could you check that please? I failed to reproduce your problem, >> > maybe I >> > did something different? >> > >> > (master checked out) >> > /tmp/grub $ /path/to/grub-src/configure --with-platform=efi >> > /tmp/grub $ make -j12 # success >> > (applied my three patches) >> > /tmp/grub $ make clean >> > /tmp/grub $ make -j12 # success >> > >> > Matthias. >> > >> > > On Wed, Mar 1, 2017 at 3:27 PM, Gailu Singh < >> gailu96@gmail.com <mailto:gailu96@gmail.com> >> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: >> > > >> > > Sorry for typo. I meant 8250 instead of 8050 in last email >> > > >> > > On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh < >> gailu96@gmail.com <mailto:gailu96@gmail.com> >> > > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> >> wrote: >> > > >> > > My board is Intel Oxbohill CRB (Apollo lake). On my >> board UART >> > > are not connected to PCI. >> > > >> > > I am using grub2 payload loaded by coreboot. UART >> works fine in >> > > coreboot by using memory mapped 8050 driver >> > > (https://github.com/coreboot/ >> coreboot/blob/master/src/drivers/uart/uart8250mem.c >> > <https://github.com/coreboot/coreboot/blob/master/src/drive >> rs/uart/uart8250mem.c> >> > > >> > <https://github.com/coreboot/coreboot/blob/master/src/driver >> s/uart/uart8250mem.c >> > <https://github.com/coreboot/coreboot/blob/master/src/drive >> rs/uart/uart8250mem.c>>), >> > > however when grub2 is loaded it refuses to recognize >> UART. >> > > >> > > >> > > >> > > On Wed, Mar 1, 2017 at 3:08 PM, Matthias Lange >> > > <matthias.lange@kernkonzept.com >> > <mailto:matthias.lange@kernkonzept.com> >> > > <mailto:matthias.lange@kernkonzept.com >> > <mailto:matthias.lange@kernkonzept.com>>> wrote: >> > > >> > > Hi, >> > > >> > > On 03/01/2017 08:00 AM, Andrei Borzenkov wrote: >> > > > please test patches from Matthias Lange >> > > > >> > > > https://lists.gnu.org/archive/ >> html/grub-devel/2017-02/msg00104.html >> > <https://lists.gnu.org/archive/html/grub-devel/2017-02/ >> msg00104.html> >> > > <https://lists.gnu.org/archiv >> e/html/grub-devel/2017-02/msg00104.html >> > <https://lists.gnu.org/archive/html/grub-devel/2017-02/ >> msg00104.html>> >> > > > >> > > > >> > > > On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh >> > <gailu96@gmail.com <mailto:gailu96@gmail.com> >> > <mailto:gailu96@gmail.com <mailto:gailu96@gmail.com>>> wrote: >> > > >> Hi Experts, >> > > >> >> > > >> I am using GRUB2 on intel apollo lake board. >> > This board does not have IO >> > > >> mapped uart instead it has 8250 memory mapped >> UART. >> > > >> > > Could you share some details about the board? >> > > >> > > >> GRUB2 does not recognize memory mapped uart and >> > gives error ("serial port >> > > >> COM0 not found). There is a 8250 memory mapped >> > driver available in coreboot. >> > > >> Is it possible to port that driver to Grub2? >> > > >> > > My patch set adds support for 8250 MMIO PCI cards. >> > Is the >> > > UART on your >> > > board connected via PCI? >> > > >> > > Best, >> > > Matthias. >> >> >> -- >> Matthias Lange, matthias.lange@kernkonzept.com, +49-351-41 888 614 >> >> Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. >> Geschäftsführer: Dr.-Ing. Michael Hohmuth >> >> > [-- Attachment #2: Type: text/html, Size: 21043 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: 8250 memory mapped UART 2017-03-27 17:59 ` Gailu Singh @ 2017-03-27 18:31 ` Lennart Sorensen 0 siblings, 0 replies; 15+ messages in thread From: Lennart Sorensen @ 2017-03-27 18:31 UTC (permalink / raw) To: The development of GNU GRUB; +Cc: Matthias Lange On Mon, Mar 27, 2017 at 11:29:48PM +0530, Gailu Singh wrote: > Can you please let me know how following three values are calculated in > your patch. I am trying to understand how do I change it for my board. > > port->board.base_baud = 4000000; > port->board.port_offset = 0x200; > port->board.base_offset = 0x1000; I would think this means: The configuration registers for the ports starts at the PCI base address of the device + 0x1000, and then each additional port is 0x200 above that (so port 2 would be at 0x1200 above the base address). A base_baud of 4000000 would normally mean the UART is fed from a 64MHz clock source. Pretty sure every uart I have used, the base_baud was 1/16th of the clock input (except some cases on the AM57xx where it uses 1/13th as far as I recall. It's a bit odd sometimes). Many PC boards in the past have used either 1.8432MHz or sometimes 14.7456 MHz, since that gives you perfect 115200 for the first one, and 921600 for the second one, as well as all integer divisions of those. After all with a base_baud of 4000000, a UART that only does integer divisions would give you 117647 when you ask for 115200, which is generally close enough. Of course some newer designs allow fractional divisions and can hence generate rather good results even with a non ideal input clock. -- Len Sorensen ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2017-03-27 18:31 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-03-01 5:53 8250 memory mapped UART Gailu Singh 2017-03-01 6:15 ` Fwd: " Gailu Singh 2017-03-01 7:00 ` Andrei Borzenkov 2017-03-01 9:38 ` Matthias Lange 2017-03-01 9:51 ` Gailu Singh 2017-03-01 9:57 ` Gailu Singh 2017-03-01 10:32 ` Gailu Singh 2017-03-01 10:57 ` Matthias Lange 2017-03-01 11:04 ` Gailu Singh 2017-03-03 12:03 ` Gailu Singh 2017-03-03 13:41 ` Matthias Lange 2017-03-03 14:07 ` Gailu Singh 2017-03-24 17:29 ` Gailu Singh 2017-03-27 17:59 ` Gailu Singh 2017-03-27 18:31 ` Lennart Sorensen
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