[igt-dev] [PATCH i-g-t 7/8] igt/i915/i915_pm_dc: DC3CO PSR2 helpers

Jeevan B
2019-09-12T08:18:08Z

From: Anshuman Gupta <anshuman.gupta@intel.com>

Add DC3CO IGT validation prerequisites stuff
so a we can enable DC3CO IGT tests.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
tests/i915/i915_pm_dc.c | 63 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 58 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index 86c12ad..c1b03a9 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -36,6 +36,10 @@
/* DC State Flags */
#define CHECK_DC5 1
#define CHECK_DC6 2
+#define CHECK_DC3CO 4
+
+/* PSR2 status 9th bit is the PSR2 idle frame indication */
+#define PSR2_IDLE_FRMAE_STS_MASK (1 << 9)

typedef struct {
int drm_fd;
@@ -88,6 +92,46 @@ static bool edp_psr_sink_support(data_t *data)
return strstr(buf, "Sink support: yes");
}

+static bool edp_psr2_enabled(data_t *data)
+
+{
+ char buf[512];
+
+ igt_debugfs_simple_read(data->debugfs_fd, "i915_edp_psr_status",
+ buf, sizeof(buf));
+
+ if (data->op_psr_mode == PSR_MODE_2)
+ return strstr(buf, "PSR mode: PSR2 enabled");
+
+ return false;
+}
+
+static uint32_t get_psr2_status(int debugfs_fd)
+{
+ char buf[512];
+ char *str;
+ uint32_t psr2_sts;
+ int ret;
+
+ igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status",
+ buf, sizeof(buf));
+
+ if (strstr(buf, "PSR mode: PSR2 enabled"))
+ str = strstr(buf, "SLEEP");
+ if (!str)
+ return 0;
+
+ ret = sscanf(str + 6, "%*c%*c%*c%x%*c", &psr2_sts);
+ igt_debug("psr2 status 0x%x\n", psr2_sts);
+ igt_assert_eq(ret, 1);
+}
+
+static bool psr2_idle_wait_entry(int debugfs_fd)
+{
+ return igt_wait((get_psr2_status(debugfs_fd) &
+ PSR2_IDLE_FRMAE_STS_MASK), 500, 20);
+}
+
static void cleanup_dc_psr(data_t *data)
{
igt_plane_t *primary;
@@ -141,12 +185,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
str = strstr(buf, "DC3 -> DC5 count");
else if (dc_flag & CHECK_DC6)
str = strstr(buf, "DC5 -> DC6 count");
+ else if (dc_flag & CHECK_DC3CO)
+ str = strstr(buf, "DC3CO count");

- /* Check DC5/DC6 counter is available for the platform.
+ /* Check DC counter is available for the platform.
* Skip the test if counter is not available.
*/
- igt_skip_on_f(!str, "DC%d counter is not available\n",
- dc_flag & CHECK_DC5 ? 5 : 6);
+ if (dc_flag & CHECK_DC3CO)
+ igt_skip_on_f(!str, "DC3CO counter is not available\n");
+ else
+ igt_skip_on_f(!str, "DC%d counter is not available\n",
+ dc_flag & CHECK_DC5 ? 5 : 6);
+
return get_dc_counter(str);
}

@@ -158,9 +208,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)

static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
{
+ char tmp[64];
+
+ snprintf(tmp, sizeof(tmp), "%s", dc_flag & CHECK_DC3CO ? "DC3CO" :
+ (dc_flag & CHECK_DC5 ? "DC5" : "DC6"));
igt_assert_f(dc_state_wait_entry(drm_fd, dc_flag, prev_dc_count),
- "DC%d state is not achieved\n",
- dc_flag & CHECK_DC5 ? 5 : 6);
+ "%s state is not achieved\n", tmp);
}

static void test_dc_state_psr(data_t *data, int dc_flag)