* [Intel-gfx] [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence
2018-07-23 20:07 [Intel-gfx] [PATCH i-g-t 1/4] lib: Don't assert all KMS drivers support edid_override Chris Wilson
@ 2018-07-23 20:07 ` Chris Wilson
2018-07-25 8:17 ` [igt-dev] " Katarzyna Dec
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 3/4] igt/gem_exec_schedule: Trim deep runtime Chris Wilson
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Modernise the test to use igt's ioctl library as opposed to the
antiquated libdrm_intel.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_tiled_fence_blits.c | 188 ++++++++++++++++++++--------------
1 file changed, 110 insertions(+), 78 deletions(-)
diff --git a/tests/gem_tiled_fence_blits.c b/tests/gem_tiled_fence_blits.c
index 693e96cec..5c1e1a68a 100644
--- a/tests/gem_tiled_fence_blits.c
+++ b/tests/gem_tiled_fence_blits.c
@@ -42,54 +42,38 @@
*/
#include "igt.h"
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-
-#include <drm.h>
-
-#include "intel_bufmgr.h"
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-enum {width=512, height=512};
-static const int bo_size = width * height * 4;
+#include "igt_x86.h"
+
+enum { width = 512, height = 512 };
static uint32_t linear[width * height];
+static const int bo_size = sizeof(linear);
-static drm_intel_bo *
-create_bo(int fd, uint32_t start_val)
+static uint32_t create_bo(int fd, uint32_t start_val)
{
- drm_intel_bo *bo;
- uint32_t tiling = I915_TILING_X;
- int ret, i;
+ uint32_t handle;
+ uint32_t *ptr;
- bo = drm_intel_bo_alloc(bufmgr, "tiled bo", bo_size, 4096);
- ret = drm_intel_bo_set_tiling(bo, &tiling, width * 4);
- igt_assert_eq(ret, 0);
- igt_assert(tiling == I915_TILING_X);
+ handle = gem_create(fd, bo_size);
+ gem_set_tiling(fd, handle, I915_TILING_X, width * 4);
/* Fill the BO with dwords starting at start_val */
- for (i = 0; i < width * height; i++)
- linear[i] = start_val++;
-
- gem_write(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_WRITE);
+ for (int i = 0; i < width * height; i++)
+ ptr[i] = start_val++;
+ munmap(ptr, bo_size);
- return bo;
+ return handle;
}
-static void
-check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
+static void check_bo(int fd, uint32_t handle, uint32_t start_val)
{
- int i;
+ uint32_t *ptr;
- gem_read(fd, bo->handle, 0, linear, sizeof(linear));
+ ptr = gem_mmap__gtt(fd, handle, bo_size, PROT_READ);
+ igt_memcpy_from_wc(linear, ptr, bo_size);
+ munmap(ptr, bo_size);
- for (i = 0; i < width * height; i++) {
+ for (int i = 0; i < width * height; i++) {
igt_assert_f(linear[i] == start_val,
"Expected 0x%08x, found 0x%08x "
"at offset 0x%08x\n",
@@ -98,73 +82,122 @@ check_bo(int fd, drm_intel_bo *bo, uint32_t start_val)
}
}
+static uint32_t
+create_batch(int fd, struct drm_i915_gem_relocation_entry *reloc)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const bool has_64b_reloc = gen >= 8;
+ uint32_t *batch;
+ uint32_t handle;
+ uint32_t pitch;
+ int i = 0;
+
+ handle = gem_create(fd, 4096);
+ batch = gem_mmap__cpu(fd, handle, 0, 4096, PROT_WRITE);
+
+ batch[i] = (XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB);
+ if (gen >= 4) {
+ batch[i] |= (XY_SRC_COPY_BLT_SRC_TILED |
+ XY_SRC_COPY_BLT_DST_TILED);
+ pitch = width;
+ } else {
+ pitch = 4 * width;
+ }
+ batch[i++] |= 6 + 2 * has_64b_reloc;
+
+ batch[i++] = 3 << 24 | 0xcc << 16 | pitch;
+ batch[i++] = 0; /* dst (x1, y1) */
+ batch[i++] = height << 16 | width; /* dst (x2 y2) */
+ reloc[0].offset = sizeof(*batch) * i;
+ reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = 0; /* src (x1, y1) */
+ batch[i++] = pitch;
+ reloc[1].offset = sizeof(*batch) * i;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ batch[i++] = 0;
+ if (has_64b_reloc)
+ batch[i++] = 0;
+
+ batch[i++] = MI_BATCH_BUFFER_END;
+ munmap(batch, 4096);
+
+ return handle;
+}
+
static void run_test(int fd, int count)
{
- drm_intel_bo **bo;
- uint32_t *bo_start_val;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_execbuffer2 eb;
+ uint32_t *bo, *bo_start_val;
uint32_t start = 0;
- int i;
+
+ memset(reloc, 0, sizeof(reloc));
+ memset(obj, 0, sizeof(obj));
+ obj[2].handle = create_batch(fd, reloc);
+ obj[2].relocs_ptr = to_user_pointer(reloc);
+ obj[2].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(&eb, 0, sizeof(eb));
+ eb.buffers_ptr = to_user_pointer(obj);
+ eb.buffer_count = ARRAY_SIZE(obj);
+ if (intel_gen(intel_get_drm_devid(fd)) >= 6)
+ eb.flags = I915_EXEC_BLT;
count |= 1;
igt_info("Using %d 1MiB buffers\n", count);
- bo = malloc(count * sizeof(*bo));
- bo_start_val = malloc(count * sizeof(*bo_start_val));
- igt_assert(bo && bo_start_val);
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+ bo = malloc(count * (sizeof(*bo) + sizeof(*bo_start_val)));
+ igt_assert(bo);
+ bo_start_val = bo + count;
- for (i = 0; i < count; i++) {
+ for (int i = 0; i < count; i++) {
bo[i] = create_bo(fd, start);
bo_start_val[i] = start;
-
- /*
- igt_info("Creating bo %d\n", i);
- check_bo(bo[i], bo_start_val[i]);
- */
-
start += width * height;
}
- for (i = 0; i < count; i++) {
- int src = count - i - 1;
- intel_copy_bo(batch, bo[i], bo[src], bo_size);
- bo_start_val[i] = bo_start_val[src];
+ for (int dst = 0; dst < count; dst++) {
+ int src = count - dst - 1;
+
+ if (src == dst)
+ continue;
+
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
+
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count * 4; i++) {
+ for (int i = 0; i < count * 4; i++) {
int src = random() % count;
int dst = random() % count;
if (src == dst)
continue;
- intel_copy_bo(batch, bo[dst], bo[src], bo_size);
- bo_start_val[dst] = bo_start_val[src];
+ reloc[0].target_handle = obj[0].handle = bo[dst];
+ reloc[1].target_handle = obj[1].handle = bo[src];
- /*
- check_bo(bo[dst], bo_start_val[dst]);
- igt_info("%d: copy bo %d to %d\n", i, src, dst);
- */
+ gem_execbuf(fd, &eb);
+ bo_start_val[dst] = bo_start_val[src];
}
- for (i = 0; i < count; i++) {
- /*
- igt_info("check %d\n", i);
- */
+ for (int i = 0; i < count; i++) {
check_bo(fd, bo[i], bo_start_val[i]);
-
- drm_intel_bo_unreference(bo[i]);
- bo[i] = NULL;
+ gem_close(fd, bo[i]);
}
-
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
-
- free(bo_start_val);
free(bo);
+
+ gem_close(fd, obj[2].handle);
}
#define MAX_32b ((1ull << 32) - 4096)
@@ -178,9 +211,8 @@ igt_main
igt_require_gem(fd);
}
- igt_subtest("basic") {
+ igt_subtest("basic")
run_test (fd, 2);
- }
/* the rest of the tests are too long for simulation */
igt_skip_on_simulation();
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Intel-gfx] [PATCH i-g-t 3/4] igt/gem_exec_schedule: Trim deep runtime
2018-07-23 20:07 [Intel-gfx] [PATCH i-g-t 1/4] lib: Don't assert all KMS drivers support edid_override Chris Wilson
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence Chris Wilson
@ 2018-07-23 20:07 ` Chris Wilson
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects Chris Wilson
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Time the runtime for emitting deep dependency tree, while keeping it
full of umpteen thousand requests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_schedule.c | 83 +++++++++++++++++++++++++++++++++------
1 file changed, 70 insertions(+), 13 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 43ea97e61..0462ce84f 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -748,21 +748,29 @@ static void preemptive_hang(int fd, unsigned ring)
static void deep(int fd, unsigned ring)
{
#define XS 8
- const unsigned int nreq = MAX_PRIO - MIN_PRIO;
- const unsigned size = ALIGN(4*nreq, 4096);
+ const unsigned int max_req = MAX_PRIO - MIN_PRIO;
+ const unsigned size = ALIGN(4*max_req, 4096);
struct timespec tv = {};
IGT_CORK_HANDLE(cork);
+ unsigned int nreq;
uint32_t plug;
uint32_t result, dep[XS];
uint32_t expected = 0;
uint32_t *ptr;
uint32_t *ctx;
+ int dep_nreq;
+ int n;
ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
ctx[n] = gem_context_create(fd);
}
+ nreq = gem_measure_ring_inflight(fd, ring, 0) / (4 * XS) * MAX_CONTEXTS;
+ if (nreq > max_req)
+ nreq = max_req;
+ igt_info("Using %d requests (prio range %d)\n", nreq, max_req);
+
result = gem_create(fd, size);
for (int m = 0; m < XS; m ++)
dep[m] = gem_create(fd, size);
@@ -774,7 +782,7 @@ static void deep(int fd, unsigned ring)
const uint32_t bbe = MI_BATCH_BUFFER_END;
memset(obj, 0, sizeof(obj));
- for (int n = 0; n < XS; n++)
+ for (n = 0; n < XS; n++)
obj[n].handle = dep[n];
obj[XS].handle = result;
obj[XS+1].handle = gem_create(fd, 4096);
@@ -784,7 +792,7 @@ static void deep(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = XS + 2;
execbuf.flags = ring;
- for (int n = 0; n < MAX_CONTEXTS; n++) {
+ for (n = 0; n < MAX_CONTEXTS; n++) {
execbuf.rsvd1 = ctx[n];
gem_execbuf(fd, &execbuf);
}
@@ -795,15 +803,62 @@ static void deep(int fd, unsigned ring)
plug = igt_cork_plug(&cork, fd);
/* Create a deep dependency chain, with a few branches */
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 8; n++) {
- uint32_t context = ctx[n % MAX_CONTEXTS];
- gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 2; n++) {
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[3];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffers_ptr = to_user_pointer(obj),
+ .buffer_count = 3,
+ .flags = ring | (gen < 6 ? I915_EXEC_SECURE : 0),
+ .rsvd1 = ctx[n % MAX_CONTEXTS],
+ };
+ uint32_t batch[16];
+ int i;
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = plug;
+
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = sizeof(uint32_t) * n;
+ reloc.read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc.write_domain = I915_GEM_DOMAIN_RENDER;
+ obj[2].handle = gem_create(fd, 4096);
+ obj[2].relocs_ptr = to_user_pointer(&reloc);
+ obj[2].relocation_count = 1;
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = reloc.delta;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = reloc.delta;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = reloc.delta;
+ }
+ batch[++i] = eb.rsvd1;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[2].handle, 0, batch, sizeof(batch));
- for (int m = 0; m < XS; m++)
- store_dword(fd, context, ring, dep[m], 4*n, context, plug, I915_GEM_DOMAIN_INSTRUCTION);
+ gem_context_set_priority(fd, eb.rsvd1, MAX_PRIO - nreq + n);
+ for (int m = 0; m < XS; m++) {
+ obj[1].handle = dep[m];
+ reloc.target_handle = obj[1].handle;
+ gem_execbuf(fd, &eb);
+ }
+ gem_close(fd, obj[2].handle);
}
+ igt_info("First deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
+ dep_nreq = n;
- for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 6; n++) {
+ for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 4; n++) {
uint32_t context = ctx[n % MAX_CONTEXTS];
gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
@@ -813,12 +868,14 @@ static void deep(int fd, unsigned ring)
}
expected = context;
}
+ igt_info("Second deptree: %d requests [%.3fs]\n",
+ n * XS, 1e-9*igt_nsec_elapsed(&tv));
unplug_show_queue(fd, &cork, ring);
gem_close(fd, plug);
igt_require(expected); /* too slow */
- for (int n = 0; n < MAX_CONTEXTS; n++)
+ for (n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
for (int m = 0; m < XS; m++) {
@@ -827,7 +884,7 @@ static void deep(int fd, unsigned ring)
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_close(fd, dep[m]);
- for (int n = 0; n < nreq; n++)
+ for (n = 0; n < dep_nreq; n++)
igt_assert_eq_u32(ptr[n], ctx[n % MAX_CONTEXTS]);
munmap(ptr, size);
}
--
2.18.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [Intel-gfx] [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects
2018-07-23 20:07 [Intel-gfx] [PATCH i-g-t 1/4] lib: Don't assert all KMS drivers support edid_override Chris Wilson
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence Chris Wilson
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 3/4] igt/gem_exec_schedule: Trim deep runtime Chris Wilson
@ 2018-07-23 20:07 ` Chris Wilson
2018-07-25 8:37 ` [igt-dev] " Katarzyna Dec
2018-07-23 20:59 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override Patchwork
2018-07-23 22:31 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2018-07-23 20:07 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Exercise O(N^2) behaviour in reading the error state, and push it to the
extreme.
Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_capture.c | 156 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 153 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index 2dc06ce43..6cc175551 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -23,6 +23,7 @@
#include "igt.h"
#include "igt_device.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
#define LOCAL_OBJECT_CAPTURE (1 << 7)
@@ -57,7 +58,7 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
igt_assert(found);
}
-static void __capture(int fd, int dir, unsigned ring, uint32_t target)
+static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -167,10 +168,149 @@ static void capture(int fd, int dir, unsigned ring)
uint32_t handle;
handle = gem_create(fd, 4096);
- __capture(fd, dir, ring, handle);
+ __capture1(fd, dir, ring, handle);
gem_close(fd, handle);
}
+static void __captureN(int fd, int dir, unsigned ring,
+ unsigned int size, int count, unsigned int flags)
+#define RANDOM 0x1
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 *obj;
+ struct drm_i915_gem_relocation_entry reloc[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t *batch, *seqno;
+ int i;
+
+ obj = calloc(count + 2, sizeof(*obj));
+ igt_assert(obj);
+
+ obj[0].handle = gem_create(fd, 4096);
+ for (i = 0; i < count; i++) {
+ obj[i + 1].handle = gem_create(fd, size);
+ obj[i + 1].flags =
+ LOCAL_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (flags & RANDOM) {
+ uint32_t *ptr;
+
+ ptr = gem_mmap__cpu(fd, obj[i + 1].handle,
+ 0, size, PROT_WRITE);
+ for (unsigned int n = 0; n < size / sizeof(*ptr); n++)
+ ptr[n] = hars_petruska_f54_1_random_unsafe();
+ munmap(ptr, size);
+ }
+ }
+
+ obj[count + 1].handle = gem_create(fd, 4096);
+ obj[count + 1].relocs_ptr = (uintptr_t)reloc;
+ obj[count + 1].relocation_count = ARRAY_SIZE(reloc);
+
+ memset(reloc, 0, sizeof(reloc));
+ reloc[0].target_handle = obj[count + 1].handle; /* recurse */
+ reloc[0].presumed_offset = 0;
+ reloc[0].offset = 5*sizeof(uint32_t);
+ reloc[0].delta = 0;
+ reloc[0].read_domains = I915_GEM_DOMAIN_COMMAND;
+ reloc[0].write_domain = 0;
+
+ reloc[1].target_handle = obj[0].handle; /* breadcrumb */
+ reloc[1].presumed_offset = 0;
+ reloc[1].offset = sizeof(uint32_t);
+ reloc[1].delta = 0;
+ reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[1].write_domain = I915_GEM_DOMAIN_RENDER;
+
+ seqno = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_READ);
+ gem_set_domain(fd, obj[0].handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ batch = gem_mmap__cpu(fd, obj[count + 1].handle, 0, 4096, PROT_WRITE);
+ gem_set_domain(fd, obj[count + 1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = 0;
+ reloc[1].offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = 0;
+ }
+ batch[++i] = 0xc0ffee;
+ if (gen < 3)
+ batch[++i] = MI_NOOP;
+
+ batch[++i] = MI_BATCH_BUFFER_START; /* not crashed? try again! */
+ if (gen >= 8) {
+ batch[i] |= 1 << 8 | 1;
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 6) {
+ batch[i] |= 1 << 8;
+ batch[++i] = 0;
+ } else {
+ batch[i] |= 2 << 6;
+ batch[++i] = 0;
+ if (gen < 4) {
+ batch[i] |= 1;
+ reloc[0].delta = 1;
+ }
+ }
+ munmap(batch, 4096);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = (uintptr_t)obj;
+ execbuf.buffer_count = count + 2;
+ execbuf.flags = ring;
+ if (gen > 3 && gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+ gem_execbuf(fd, &execbuf);
+
+ /* Wait for the request to start */
+ while (*(volatile uint32_t *)seqno != 0xc0ffee)
+ igt_assert(gem_bo_busy(fd, obj[0].handle));
+ munmap(seqno, 4096);
+
+ igt_force_gpu_reset(fd);
+
+ gem_sync(fd, obj[count + 1].handle);
+ gem_close(fd, obj[count + 1].handle);
+ for (i = 0; i < count; i++)
+ gem_close(fd, obj[i + 1].handle);
+ gem_close(fd, obj[0].handle);
+}
+
+static void many(int fd, int dir, unsigned int flags)
+{
+ uint64_t ram, gtt;
+ unsigned long count;
+ char *error;
+
+ gtt = (gem_aperture_size(fd) >> 20) / 4;
+ ram = intel_get_avail_ram_mb() / 4;
+ igt_debug("Available objects in GTT:%"PRIu64", RAM:%"PRIu64"\n",
+ gtt, ram);
+
+ count = min(gtt, ram);
+ igt_require(count > 1);
+
+ intel_require_memory(count, 2 << 20, CHECK_RAM);
+
+ __captureN(fd, dir, 0, 2 << 20, count, flags);
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+
+ igt_assert(error);
+ igt_debug("%s\n", error);
+}
+
static void userptr(int fd, int dir)
{
uint32_t handle;
@@ -179,7 +319,7 @@ static void userptr(int fd, int dir)
igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
- __capture(fd, dir, 0, handle);
+ __capture1(fd, dir, 0, handle);
gem_close(fd, handle);
free(ptr);
@@ -236,6 +376,16 @@ igt_main
}
}
+ igt_subtest_f("many-zero") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, 0);
+ }
+
+ igt_subtest_f("many-random") {
+ igt_require(gem_can_store_dword(fd, 0));
+ many(fd, dir, RANDOM);
+ }
+
/* And check we can read from different types of objects */
igt_subtest_f("userptr") {
--
2.18.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override
2018-07-23 20:07 [Intel-gfx] [PATCH i-g-t 1/4] lib: Don't assert all KMS drivers support edid_override Chris Wilson
` (2 preceding siblings ...)
2018-07-23 20:07 ` [Intel-gfx] [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects Chris Wilson
@ 2018-07-23 20:59 ` Patchwork
2018-07-23 22:31 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-07-23 20:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override
URL : https://patchwork.freedesktop.org/series/47084/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4521 -> IGTPW_1633 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47084/revisions/1/mbox/
== Known issues ==
Here are the changes found in IGTPW_1633 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_module_reload@basic-reload-inject:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248) +1
igt@gem_ringfill@basic-default-fd:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719)
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: PASS -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: NOTRUN -> INCOMPLETE (fdo#103713)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-ilk-650: FAIL (fdo#104008) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
== Participating hosts (47 -> 43) ==
Additional (1): fi-bsw-kefka
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* IGT: IGT_4570 -> IGTPW_1633
CI_DRM_4521: a4ebbd84c682fd30edbde6ac0e48d150d4c5c066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1633: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1633/
IGT_4570: 65cdccdc7bcbb791d791aeeeecb784a382110a3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_capture@many-random
+igt@gem_exec_capture@many-zero
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1633/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override
2018-07-23 20:07 [Intel-gfx] [PATCH i-g-t 1/4] lib: Don't assert all KMS drivers support edid_override Chris Wilson
` (3 preceding siblings ...)
2018-07-23 20:59 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override Patchwork
@ 2018-07-23 22:31 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-07-23 22:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,1/4] lib: Don't assert all KMS drivers support edid_override
URL : https://patchwork.freedesktop.org/series/47084/
State : failure
== Summary ==
= CI Bug Log - changes from IGT_4570_full -> IGTPW_1633_full =
== Summary - FAILURE ==
Serious unknown changes coming with IGTPW_1633_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_1633_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47084/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_1633_full:
=== IGT changes ===
==== Possible regressions ====
igt@gem_eio@in-flight-contexts-10ms:
shard-snb: PASS -> FAIL
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-apl: SKIP -> PASS +3
igt@gem_exec_schedule@deep-bsd:
shard-glk: SKIP -> PASS +3
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: PASS -> SKIP +1
igt@gem_mocs_settings@mocs-rc6-bsd1:
shard-kbl: SKIP -> PASS
igt@kms_atomic_interruptible@legacy-pageflip:
shard-snb: SKIP -> PASS +1
== Known issues ==
Here are the changes found in IGTPW_1633_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
{igt@gem_exec_capture@many-random}:
shard-hsw: NOTRUN -> INCOMPLETE (fdo#103540)
shard-snb: NOTRUN -> INCOMPLETE (fdo#105411)
{igt@gem_exec_capture@many-zero}:
shard-apl: NOTRUN -> INCOMPLETE (fdo#103927) +1
shard-kbl: NOTRUN -> INCOMPLETE (fdo#103665) +1
shard-glk: NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133) +1
igt@gem_exec_schedule@pi-ringfull-vebox:
shard-glk: NOTRUN -> FAIL (fdo#103158)
igt@gem_softpin@noreloc-s3:
shard-glk: PASS -> FAIL (fdo#103375)
igt@kms_busy@extended-modeset-hang-newfb-render-d:
shard-snb: SKIP -> INCOMPLETE (fdo#105411)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
shard-kbl: PASS -> INCOMPLETE (fdo#103665) +1
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@gem_mmap_gtt@coherency:
shard-glk: FAIL (fdo#100587) -> SKIP +1
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-snb: FAIL (fdo#103166) -> PASS
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
igt@perf_pmu@multi-client-vcs1:
shard-snb: INCOMPLETE (fdo#105411) -> SKIP
igt@prime_vgem@coherency-gtt:
shard-apl: FAIL (fdo#100587) -> SKIP +1
igt@testdisplay:
shard-glk: INCOMPLETE (fdo#103359, fdo#107093, k.org#198133) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#107093 https://bugs.freedesktop.org/show_bug.cgi?id=107093
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* IGT: IGT_4570 -> IGTPW_1633
* Linux: CI_DRM_4519 -> CI_DRM_4521
CI_DRM_4519: f14c0ec8fe9acce6fd1be84766f854ab8874eb33 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_4521: a4ebbd84c682fd30edbde6ac0e48d150d4c5c066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1633: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1633/
IGT_4570: 65cdccdc7bcbb791d791aeeeecb784a382110a3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1633/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 8+ messages in thread