From: Tvrtko Ursulin <tursulin@ursulin.net>
To: igt-dev@lists.freedesktop.org
Cc: Intel-gfx@lists.freedesktop.org,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: [igt-dev] [PATCH i-g-t 09/17] gem_wsim: Submit fence support
Date: Thu, 18 Oct 2018 16:28:07 +0100 [thread overview]
Message-ID: <20181018152815.31816-10-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
benchmarks/gem_wsim.c | 20 ++++++++++++++++----
benchmarks/wsim/README | 17 +++++++++++++++++
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 0010f46c357d..a77a322ee309 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -86,6 +86,7 @@ enum w_type
struct deps
{
int nr;
+ bool submit_fence;
int *list;
};
@@ -254,17 +255,23 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc)
w->data_deps.list == w->fence_deps.list);
while ((token = strtok_r(tstart, "/", &tctx)) != NULL) {
+ bool submit_fence = false;
char *str = token;
struct deps *deps;
int dep;
tstart = NULL;
- if (strlen(token) > 1 && token[0] == 'f') {
+ if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) {
+ deps = &w->data_deps;
+ } else {
+ if (str[0] == 's')
+ submit_fence = true;
+ else if (str[0] != 'f')
+ return -1;
+
deps = &w->fence_deps;
str++;
- } else {
- deps = &w->data_deps;
}
dep = atoi(str);
@@ -282,6 +289,7 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc)
sizeof(*deps->list) * deps->nr);
igt_assert(deps->list);
deps->list[deps->nr - 1] = dep;
+ deps->submit_fence = submit_fence;
}
}
@@ -1891,7 +1899,11 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine,
igt_assert(tgt >= 0 && tgt < w->idx);
igt_assert(wrk->steps[tgt].emit_fence > 0);
- w->eb.flags |= I915_EXEC_FENCE_IN;
+ if (w->fence_deps.submit_fence)
+ w->eb.flags |= I915_EXEC_FENCE_SUBMIT;
+ else
+ w->eb.flags |= I915_EXEC_FENCE_IN;
+
w->eb.rsvd2 = wrk->steps[tgt].emit_fence;
}
diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README
index 205cd6c93afb..4786f116b4ac 100644
--- a/benchmarks/wsim/README
+++ b/benchmarks/wsim/README
@@ -114,6 +114,23 @@ runnable. When the second RCS batch completes the standalone fence is signaled
which allows the two VCS batches to be executed. Finally we wait until the both
VCS batches have completed before starting the (optional) next iteration.
+Submit fences
+-------------
+
+Submit fences are a type of input fence which are signalled when the originating
+batch buffer is submitted to the GPU. (In contrary to normal sync fences, which
+are signalled when completed.)
+
+Submit fences have the identical syntax as the sync fences with the lower-case
+'s' being used to select them. Eg:
+
+ 1.RCS.500-1000.0.0
+ 1.VCS1.3000.s-1.0
+ 1.VCS2.3000.s-2.0
+
+Here VCS1 and VCS2 batches will only be submitted for executing once the RCS
+batch enters the GPU.
+
Context priority
----------------
--
2.17.1
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next prev parent reply other threads:[~2018-10-18 15:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 15:27 [igt-dev] [PATCH i-g-t 00/17] Media scalability tooling Tvrtko Ursulin
2018-10-18 15:27 ` [Intel-gfx] [PATCH i-g-t 01/17] lib: Update uapi headers Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 02/17] trace.pl: Virtual engine support Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 03/17] trace.pl: Virtual engine preemption support Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 04/17] wsim/media-bench: i915 balancing Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 05/17] gem_wsim: Use IGT uapi headers Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 06/17] gem_wsim: Fix shadowed local Tvrtko Ursulin
2018-10-18 15:28 ` [Intel-gfx] [PATCH i-g-t 07/17] gem_wsim: Factor out common error handling Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 08/17] gem_wsim: More wsim_err Tvrtko Ursulin
2018-10-18 15:28 ` Tvrtko Ursulin [this message]
2018-10-18 15:28 ` [Intel-gfx] [PATCH i-g-t 10/17] gem_wsim: Extract str to engine lookup Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 11/17] gem_wsim: Engine map support Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 12/17] gem_wsim: Save some lines by changing to implicit NULL checking Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 13/17] gem_wsim: Compact int command parsing with a macro Tvrtko Ursulin
2018-10-18 15:28 ` [Intel-gfx] [PATCH i-g-t 14/17] gem_wsim: Engine map load balance command Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 15/17] gem_wsim: Engine bond command Tvrtko Ursulin
2018-10-18 21:48 ` Chris Wilson
2018-10-26 11:11 ` Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 16/17] gem_wsim: Some more example workloads Tvrtko Ursulin
2018-10-18 15:28 ` [igt-dev] [PATCH i-g-t 17/17] gem_wsim: Infinite batch support Tvrtko Ursulin
2018-10-18 15:37 ` [igt-dev] ✗ Fi.CI.BAT: failure for Media scalability tooling Patchwork
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