[igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Andi Shyti <andi.shyti@intel.com>]

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The library provides three helper functions:

1. gem_topology_has_engine(): checks if the engine is present by
   querying the driver in a way that the caller function wouldn't
   know if the above ioctls are implemented.

2. gem_set_eb_flags(): sets the execution buffer flag depending
   whether it refers to context-engine mapping or not.

3. gem_context_execbuf(): is a wrapper that executes the buffer
   in a way that the calling function doesn't know about the
   ioctls in the driver.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 210 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  52 ++++++++
 lib/meson.build                |   1 +
 4 files changed, 265 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..e836b3745e04
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = SIZEOF_QUERY;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void set_ctx_param_engines(struct intel_engine_data *ed)
+{
+	struct i915_context_param_engines *ctx_engine;
+	struct drm_i915_gem_context_param ctx_param;
+	uint8_t buff[SIZEOF_CTX_PARAM] = { };
+	int i;
+
+	ctx_engine = (struct i915_context_param_engines *) buff;
+
+	ctx_engine->extensions = 0;
+	for (i = 0; i < ed->nengines; i++) {
+		ctx_engine->class_instance[i].engine_class =
+							ed->engines[i].class;
+		ctx_engine->class_instance[i].engine_instance =
+							ed->engines[i].instance;
+	}
+
+	ctx_param.size   = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
+	ctx_param.value  = to_user_pointer(ctx_engine);
+	ctx_param.ctx_id = ed->ctx;
+	ctx_param.param  = I915_CONTEXT_PARAM_ENGINES;
+
+	gem_context_set_param(ed->fd, &ctx_param);
+}
+
+static void init_engine_list(struct intel_engine_data *ed)
+{
+	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
+	struct drm_i915_query_engine_info *query_engine;
+	unsigned char query_buffer[SIZEOF_QUERY] = { };
+	int i;
+
+	query_engine = (struct drm_i915_query_engine_info *) query_buffer;
+	query_engines(ed->fd, query_engine);
+
+	for (i = 0; i < query_engine->num_engines; i++) {
+		char *name;
+		__u16 class = query_engine->engines[i].engine_class;
+		__u16 instance = query_engine->engines[i].engine_instance;
+
+		ed->engines[i].class = class;
+		ed->engines[i].instance = instance;
+
+		/* if we don't recognise the class, then we mark it as "unk" */
+		if (class >= ARRAY_SIZE(class_names))
+			igt_assert(asprintf(&name, "unk-%d:%d",
+					    class, instance) > 0);
+		else
+			igt_assert(asprintf(&name, "%s%d",
+					    class_names[class], instance) > 0);
+
+		ed->engines[i].name = name;
+	}
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+		.ctx_id = ctx_id,
+	};
+	struct intel_engine_data engine_data = {
+		.n = 0,
+		.fd = fd,
+		.ctx = ctx_id,
+	};
+
+	if (__gem_context_get_param(fd, &ctx_param)) {
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_engine_class_instance(e2) {
+			if (!gem_has_engine(fd, e2->class, e2->instance))
+				continue;
+
+			engine_data.engines[engine_data.nengines].name =
+								e2->name;
+			engine_data.engines[engine_data.nengines].instance =
+								e2->instance;
+			engine_data.engines[engine_data.nengines].class =
+								e2->class;
+			engine_data.nengines++;
+		}
+
+		return engine_data;
+	}
+
+	init_engine_list(&engine_data);
+
+	if (ctx_param.size == sizeof(struct i915_context_param_engines))
+		set_ctx_param_engines(&engine_data);
+
+	return engine_data;
+}
+
+bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
+			     uint8_t i, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	if (!e)
+		return false;
+
+	if (__gem_context_get_param(fd, &ctx_param))
+		return gem_has_engine(fd, e->class, e->instance);
+
+	return gem_context_has_engine(fd, i, ctx);
+}
+
+void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
+		      struct intel_execution_engine2 e2,
+		      uint8_t engine, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	if (__gem_context_get_param(fd, &ctx_param)) {
+		eb->flags |= (I915_EXEC_RING_MASK & engine);
+		eb->rsvd1 = ctx;
+	} else {
+		eb->flags |= gem_class_instance_to_eb_flags(fd, e2.class,
+							    e2.instance);
+	}
+}
+
+int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			  struct intel_execution_engine2 e2,
+			  uint8_t engine, uint32_t ctx)
+{
+	gem_set_eb_flags(fd, eb, e2, engine, ctx);
+	return __gem_execbuf(fd, eb);
+}
+
+void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			 struct intel_execution_engine2 e2,
+			 uint8_t index_map, uint32_t ctx)
+{
+	igt_assert_eq(__gem_context_execbuf(fd, eb, e2, index_map, ctx), 0);
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..657b9397a181
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+
+struct intel_engine_data {
+	int fd;
+	uint32_t ctx;
+
+	uint32_t nengines;
+	uint32_t n;
+	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
+			     uint8_t i, uint32_t ctx);
+
+void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
+		      struct intel_execution_engine2 e2,
+		      uint8_t engine, uint32_t ctx);
+int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			  struct intel_execution_engine2 e2,
+			  uint8_t engine, uint32_t ctx);
+void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			 struct intel_execution_engine2 e2,
+			 uint8_t index_map, uint32_t ctx);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev