Re: [igt-dev] [PATCH i-g-t 4/5] lib/rendercopy: Configure MOCS more consistently

Ville Syrjälä
2019-04-26T19:27:41Z

On Fri, Apr 26, 2019 at 08:18:31PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-18 20:40:42)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Unify the MOCS to be more consistently across the platforms.
> > Currently gen8+ are specifyig UC whereas earlier platforms
> > generally use PTE. Let's make everyone more or less specify
> > L3+PTE.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > lib/gen6_render.h | 9 ++++++++-
> > lib/gen7_render.h | 11 ++++++++++-
> > lib/gen8_render.h | 15 +++++++++++++++
> > lib/rendercopy_gen6.c | 2 ++
> > lib/rendercopy_gen7.c | 5 ++++-
> > lib/rendercopy_gen8.c | 7 +++++++
> > lib/rendercopy_gen9.c | 2 ++
> > 7 files changed, 48 insertions(+), 3 deletions(-)
> >
> > diff --git a/lib/gen6_render.h b/lib/gen6_render.h
> > index f45c8ae7b34a..a4c166417634 100644
> > --- a/lib/gen6_render.h
> > +++ b/lib/gen6_render.h
> > @@ -735,6 +735,12 @@
> > #define GEN6_SCRATCH_SPACE_SIZE_1M 10
> > #define GEN6_SCRATCH_SPACE_SIZE_2M 11
> >
> > +#define GEN6_MOCS_GFDT (1 << 2)
> > +#define GEN6_MOCS_PTE (0 << 0)
> > +#define GEN6_MOCS_UC (1 << 0)
> > +#define GEN6_MOCS_LLC (2 << 0)
> > +#define GEN6_MOCS_LLC_MLC (3 << 0)
> > +
> > /* The hardware supports two different modes for border color. The
> > * default (OpenGL) mode uses floating-point color channels, while the
> > * legacy mode uses 4 bytes.
> > @@ -933,7 +939,8 @@ struct gen6_surface_state {
> > } ss4;
> >
> > struct {
> > - uint32_t pad:20;
> > + uint32_t pad:16;
> > + uint32_t memory_object_control:4;
> > uint32_t y_offset:4;
> > uint32_t pad2:1;
> > uint32_t x_offset:7;
> > diff --git a/lib/gen7_render.h b/lib/gen7_render.h
> > index 4bde0d5f13ec..5dfc04d4bc2b 100644
> > --- a/lib/gen7_render.h
> > +++ b/lib/gen7_render.h
> > @@ -186,6 +186,14 @@
> >
> > #define GEN7_ARF_IP 0xA0
> >
> > +#define VLV_MOCS_SNOOP (2 << 1)
> > +#define VLV_MOCS_L3 (1 << 0)
> > +
> > +#define IVB_MOCS_GFDT (1 << 2)
> > +#define IVB_MOCS_PTE (0 << 1)
> > +#define IVB_MOCS_LLC (1 << 1)
> > +#define IVB_MOCS_L3 (1 << 0)
> > +
> > /* The hardware supports two different modes for border color. The
> > * default (OpenGL) mode uses floating-point color channels, while the
> > * legacy mode uses 4 bytes.
> > @@ -252,7 +260,8 @@ struct gen7_surface_state {
> > struct {
> > unsigned int mip_count:4;
> > unsigned int min_lod:4;
> > - unsigned int pad1:12;
> > + unsigned int pad1:8;
> > + unsigned int memory_object_control:4;
> > unsigned int y_offset:4;
> > unsigned int pad0:1;
> > unsigned int x_offset:7;
> > diff --git a/lib/gen8_render.h b/lib/gen8_render.h
> > index 7e33bea22d65..31dc01bcf57c 100644
> > --- a/lib/gen8_render.h
> > +++ b/lib/gen8_render.h
> > @@ -67,6 +67,21 @@
> > /* STATE_BASE_ADDRESS state size in pages*/
> > #define GEN8_STATE_SIZE_PAGES(x) ((x) << 12)
> >
> > +#define BDW_MOCS_PTE (0 << 5)
> > +#define BDW_MOCS_UC (1 << 5)
> > +#define BDW_MOCS_WT (2 << 5)
> > +#define BDW_MOCS_WB (3 << 5)
> > +#define BDW_MOCS_TC_ELLC (0 << 3)
> > +#define BDW_MOCS_TC_LLC (1 << 3)
> > +#define BDW_MOCS_TC_LLC_ELLC (2 << 3)
> > +#define BDW_MOCS_TC_L3_PTE (3 << 3)
> > +#define BDW_MOCS_AGE(x) ((x) << 0)
> > +
> > +#define CHV_MOCS_UC (0 << 5)
> > +#define CHV_MOCS_WB (3 << 5)
> > +#define CHV_MOCS_NO_CACHING (0 << 3)
> > +#define CHV_MOCS_L3 (3 << 3)
> > +
> > /* Shamelessly ripped from mesa */
> > struct gen8_surface_state
> > {
> > diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
> > index b90466d007f9..83c7d6941bdd 100644
> > --- a/lib/rendercopy_gen6.c
> > +++ b/lib/rendercopy_gen6.c
> > @@ -117,6 +117,8 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
> > ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE;
> > ss->ss3.tile_walk = buf->tiling == I915_TILING_Y;
> >
> > + ss->ss5.memory_object_control = GEN6_MOCS_PTE;
> > +
> > return intel_batchbuffer_subdata_offset(batch, ss);
> > }
> >
> > diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
> > index 949468427b2f..a3c8b7f36989 100644
> > --- a/lib/rendercopy_gen7.c
> > +++ b/lib/rendercopy_gen7.c
> > @@ -94,7 +94,10 @@ gen7_bind_buf(struct intel_batchbuffer *batch,
> > (igt_buf_height(buf) - 1) << GEN7_SURFACE_HEIGHT_SHIFT);
> > ss[3] = (buf->stride - 1) << GEN7_SURFACE_PITCH_SHIFT;
> > ss[4] = 0;
> > - ss[5] = 0;
> > + if (IS_VALLEYVIEW(batch->devid))
> > + ss[5] = VLV_MOCS_L3 << 16;
> > + else
> > + ss[5] = (IVB_MOCS_L3 | IVB_MOCS_PTE) << 16;
> > ss[6] = 0;
> > ss[7] = 0;
> > if (IS_HASWELL(batch->devid))
> > diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
> > index f7a33947166e..e22d8501cb55 100644
> > --- a/lib/rendercopy_gen8.c
> > +++ b/lib/rendercopy_gen8.c
> > @@ -16,6 +16,7 @@
> > #include "drmtest.h"
> > #include "intel_bufmgr.h"
> > #include "intel_batchbuffer.h"
> > +#include "intel_chipset.h"
> > #include "intel_io.h"
> > #include "rendercopy.h"
> > #include "gen8_render.h"
> > @@ -181,6 +182,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch,
> > else if (buf->tiling == I915_TILING_Y)
> > ss->ss0.tiled_mode = 3;
> >
> > + if (IS_CHERRYVIEW(batch->devid))
> > + ss->ss1.memory_object_control = CHV_MOCS_WB | CHV_MOCS_L3;
> > + else
> > + ss->ss1.memory_object_control = BDW_MOCS_PTE |
> > + BDW_MOCS_TC_L3_PTE | BDW_MOCS_AGE(0);
> > +
> > ss->ss8.base_addr = buf->bo->offset64;
> > ss->ss9.base_addr_hi = buf->bo->offset64 >> 32;
> >
> > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> > index 5c6485d750a9..259a3ca24ba5 100644
> > --- a/lib/rendercopy_gen9.c
> > +++ b/lib/rendercopy_gen9.c
> > @@ -212,6 +212,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
> > else if (buf->tiling != I915_TILING_NONE)
> > ss->ss0.tiled_mode = 3;
> >
> > + ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
> > +
> > if (buf->tiling == I915_TILING_Yf)
> > ss->ss5.trmode = 1;
> > else if (buf->tiling == I915_TILING_Ys)
>
> I never understood chv and its not-snooping snooping, but it looks
> consistent nevertheless,

IIRC my conclusion was that on chv the snoop bit always comes from the
PTE, and MOCS only controls L3.

--
Ville Syrjälä
Intel