Re: [igt-dev] [PATCH i-g-t] tests/prime_busy: Increase timeout to mind pre-silicon.

[Katarzyna Dec <katarzyna.dec@intel.com>]

On Wed, May 29, 2019 at 03:53:32PM +0200, Tomasz Lis wrote:
> From: "Lis, Tomasz" <tomasz.lis@intel.com>
> 
> On silicon, simple submission is finished much faster than in a second.
> But for pre-silicon, it is not always the case. Six seconds should be
> enough though.
> 
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mrzyglod Daniel T <daniel.t.mrzyglod@intel.com>
> Cc: Michal Winiarski <michal.winiarski@intel.com>
> Cc: Katarzyna Dec <katarzyna.dec@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>  tests/prime_busy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/prime_busy.c b/tests/prime_busy.c
> index a82acbdb..8e0f3ca6 100644
> --- a/tests/prime_busy.c
> +++ b/tests/prime_busy.c
> @@ -147,7 +147,7 @@ static void busy(int fd, unsigned ring, unsigned flags)
>  	if ((flags & HANG) == 0) {
>  		*bbe = MI_BATCH_BUFFER_END;
>  		__sync_synchronize();
> -		timeout = 1;
> +		timeout = 6;
Here you are changing timeout for all configurations that can be used -
simulation or HW and for other HW generations. I suggest we use something like:
 if (igt_run_in_simulation()) {
	timeout = 6;
 } else {
	timeout = 1;
 }

This wil allow to preserve scenario for non-simulation environment.

Kasia
>  	}
>  
>  	/* Calling busy in a loop should be enough to flush the rendering */
> -- 
> 2.14.1
> 
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