From: Ramalingam C <ramalingam.c@intel.com>
To: igt-dev <igt-dev@lists.freedesktop.org>
Subject: [igt-dev] [PATCH i-g-t] tests/i915/WA: Mark FF_MODE2 as WO for TGL
Date: Wed, 20 Nov 2019 20:27:12 +0530 [thread overview]
Message-ID: <20191120145712.27496-1-ramalingam.c@intel.com> (raw)
On TGL till B0 stepping FF_MODE2(0x6604) register is not readable. But
we need to program this register for Wa_1604555607 for better
performance. Hence to skip the verification attempt on this register
through read, we are marking this register as write only.
As of now I have marked this register as write only for gen12, we can
narrow it down to TGL <= B0, if we can retrieve the stepping of the
platform at IGT.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
cc: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/i915/gem_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index dd6316ea3b4e..57d307b9991b 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -51,8 +51,8 @@ static struct write_only_list {
unsigned int gen;
uint32_t addr;
} wo_list[] = {
- { 10, 0xE5F0 } /* WaForceContextSaveRestoreNonCoherent:cnl */
-
+ { 10, 0xE5F0 }, /* WaForceContextSaveRestoreNonCoherent:cnl */
+ { 12, 0x6604 } /* FIXME: Stepping > B0 might be readable */
/*
* FIXME: If you are contemplating adding stuff here
* consider this as a temporary solution. You need to
--
2.20.1
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next reply other threads:[~2019-11-20 14:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-20 14:57 Ramalingam C [this message]
2019-11-20 15:29 ` [igt-dev] [PATCH i-g-t] tests/i915/WA: Mark FF_MODE2 as WO for TGL Chris Wilson
2019-11-20 15:39 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-11-21 7:10 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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