[igt-dev] [PATCH i-g-t 2/4] lib/rendercopy_gen9: Add GEN12 color clear

[Mika Kahola <mika.kahola@intel.com>]

GEN12 supports color clear feature on the 3rd plane. The patch
updates rendercopy function to and buffers to support clear color.

Surface state bitgroups 12 and 13 are updated to support clear value
or depth clear value.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 lib/gen9_render.h       |  7 +++++--
 lib/igt_fb.c            |  3 +++
 lib/intel_batchbuffer.h |  3 +++
 lib/rendercopy_gen9.c   | 11 +++++++++++
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 9ee5782b..ab99563a 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -118,12 +118,15 @@ struct gen9_surface_state {
 		uint32_t aux_base_addr_hi;
 	} ss11;
 
+	/* register can be used for either
+	 * clear value or depth clear value
+	 */
 	struct {
-		uint32_t hiz_depth_clear_value;
+		uint32_t clear_address;
 	} ss12;
 
 	struct {
-		uint32_t reserved;
+		uint32_t clear_address_hi;
 	} ss13;
 
 	struct {
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1d1e0d22..53aa344a 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1936,6 +1936,9 @@ static void init_buf(struct fb_blit_upload *blit,
 		buf->aux.offset = fb->offsets[1];
 		buf->aux.stride = fb->strides[1];
 	}
+
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		buf->cc.offset = fb->offsets[2];
 }
 
 static void fini_buf(struct igt_buf *buf)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index e5f6e6d0..fc28dd55 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -234,6 +234,9 @@ struct igt_buf {
 		uint32_t offset;
 		uint32_t stride;
 	} aux;
+	struct {
+		uint32_t offset;
+	} cc;
 	/*< private >*/
 	unsigned num_tiles;
 };
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 3189594f..8f75c185 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -271,6 +271,17 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
 		assert(ret == 0);
 	}
 
+	if (buf->cc.offset) {
+		ss->ss12.clear_address = buf->bo->offset64 + buf->cc.offset;
+		ss->ss13.clear_address_hi = (buf->bo->offset64 + buf->cc.offset) >> 32;
+
+		ret = drm_intel_bo_emit_reloc(batch->bo,
+					      intel_batchbuffer_subdata_offset(batch, &ss->ss12),
+					      buf->bo, buf->cc.offset,
+					      read_domain, write_domain);
+		assert(ret == 0);
+	}
+
 	return offset;
 }
 
-- 
2.17.1

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