[igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg

Imre Deak
2019-11-29T10:38:56Z

We're only using the first instance of the render engine, but the
standard way on GEN12 to read/write engine registers is to depend on the
MMIO remapping to select the proper instance based on which command
streamer the read/write instruction was run from.

Enable the MMIO remapping to align with the standard way to do reg
read/writes.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_aux_pgtable.c | 4 ++--
lib/intel_reg.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 319b2745..2f22bb39 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -560,11 +560,11 @@ gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
if (!state)
return;

- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
OUT_RELOC(batch->bo, 0, 0, state);

- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
OUT_RELOC(batch->bo, 0, 0, state + 4);
}
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 96236828..cabfc879 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2572,6 +2572,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
+#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)

/* Flush */
#define MI_FLUSH (0x04<<23)
--
2.17.1