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From: Petri Latvala <petri.latvala@intel.com>
To: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: igt-dev@lists.freedesktop.org, Nidhi Gupta <nidhi1.gupta@intel.com>
Subject: Re: [igt-dev] [PATCH i-g-t 1/2] tests/kms_chamelium: Fix dp-mode-timings test
Date: Wed, 8 Apr 2020 12:17:04 +0300	[thread overview]
Message-ID: <20200408091704.GN9497@platvala-desk.ger.corp.intel.com> (raw)
In-Reply-To: <20200407101338.1340310-1-arkadiusz.hiler@intel.com>

On Tue, Apr 07, 2020 at 01:13:37PM +0300, Arkadiusz Hiler wrote:
> Chamelium provides us with hsync_offset value which is read form its
> receiver register described as "Hsync start edge to H active start
> edge", vsync_offest is analogous.
> 
> Let's calculate the correct things on IGT side.
> 
> v2: keep the original checks for HDMI (Petri)
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Nidhi Gupta <nidhi1.gupta@intel.com>
> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>

Why does the discrepancy exist in the first place, DP vs HDMI? Just
the receivers handled differently in chameliumd? Is this a
misunderstanding on cham side and we might get a fix later and have to
change this test again?

Oh well. Either way, we don't automatically update chameliumd and will
notice if there's a need to update tests again...

Reviewed-by: Petri Latvala <petri.latvala@intel.com>


> ---
>  tests/kms_chamelium.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/kms_chamelium.c b/tests/kms_chamelium.c
> index 77c203d3..69c9de4e 100644
> --- a/tests/kms_chamelium.c
> +++ b/tests/kms_chamelium.c
> @@ -915,10 +915,20 @@ static void check_mode(struct chamelium *chamelium, struct chamelium_port *port,
>  	chamelium_port_get_video_params(chamelium, port, &video_params);
>  
>  	mode_clock = (double) mode->clock / 1000;
> -	mode_hsync_offset = mode->hsync_start - mode->hdisplay;
> -	mode_vsync_offset = mode->vsync_start - mode->vdisplay;
> +
> +	if (chamelium_port_get_type(port) == DRM_MODE_CONNECTOR_DisplayPort) {
> +		/* this is what chamelium understands as offsets for DP */
> +		mode_hsync_offset = mode->htotal - mode->hsync_start;
> +		mode_vsync_offset = mode->vtotal - mode->vsync_start;
> +	} else {
> +		/* and this is what they are for other connectors */
> +		mode_hsync_offset = mode->hsync_start - mode->hdisplay;
> +		mode_vsync_offset = mode->vsync_start - mode->vdisplay;
> +	}
> +
>  	mode_hsync_width = mode->hsync_end - mode->hsync_start;
>  	mode_vsync_width = mode->vsync_end - mode->vsync_start;
> +
>  	mode_hsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
>  	mode_vsync_polarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
>  
> -- 
> 2.24.1
> 
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  parent reply	other threads:[~2020-04-08  9:17 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-07 10:13 [igt-dev] [PATCH i-g-t 1/2] tests/kms_chamelium: Fix dp-mode-timings test Arkadiusz Hiler
2020-04-07 10:13 ` [igt-dev] [PATCH i-g-t 2/2] HAX: add dp-mode-timings to BAT Arkadiusz Hiler
2020-04-07 11:04 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] tests/kms_chamelium: Fix dp-mode-timings test Patchwork
2020-04-07 17:15 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-08  9:17 ` Petri Latvala [this message]
2020-04-08  9:28   ` [igt-dev] [PATCH i-g-t 1/2] " Arkadiusz Hiler
  -- strict thread matches above, loose matches on Subject: below --
2020-04-07  9:00 Arkadiusz Hiler

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