From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E9CA410E375 for ; Fri, 19 May 2023 15:46:55 +0000 (UTC) From: Umesh Nerlige Ramappa To: igt-dev@lists.freedesktop.org Date: Fri, 19 May 2023 08:46:41 -0700 Message-Id: <20230519154650.3751855-8-umesh.nerlige.ramappa@intel.com> In-Reply-To: <20230519154650.3751855-1-umesh.nerlige.ramappa@intel.com> References: <20230519154650.3751855-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 07/16] intel_gpu_top: Add an array of freq and rc6 counters List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Since rc6 and frequency events are specific to a tile in multi-tile platforms, prepare support for multi-tile by storing these events in an array. Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Tvrtko Ursulin --- tools/intel_gpu_top.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index 453090c29..ae086ae12 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -88,6 +88,7 @@ struct engine { struct pmu_counter sema; }; +#define MAX_GTS 4 struct engines { unsigned int num_engines; unsigned int num_classes; @@ -107,9 +108,12 @@ struct engines { unsigned int num_imc; struct pmu_counter freq_req; + struct pmu_counter freq_req_gt[MAX_GTS]; struct pmu_counter freq_act; + struct pmu_counter freq_act_gt[MAX_GTS]; struct pmu_counter irq; struct pmu_counter rc6; + struct pmu_counter rc6_gt[MAX_GTS]; bool discrete; char *device; -- 2.36.1