From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 729A010E533 for ; Thu, 19 Oct 2023 17:53:03 +0000 (UTC) From: Melanie Lobo To: igt-dev@lists.freedesktop.org Date: Thu, 19 Oct 2023 23:36:30 +0530 Message-Id: <20231019180630.20689-1-melanie.lobo@intel.com> In-Reply-To: <20231010134540.28485-1-melanie.lobo@intel.com> References: <20231010134540.28485-1-melanie.lobo@intel.com> Subject: [igt-dev] [PATCH] tests/intel/kms_flip_scaled_crc: Add support for FP16 compressed formats List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: MTL supports FP16 format which is a binary floating-point computer number format that occupies 16 bits in computer memory. In this test platform shall render compression in display engine to receive FP16 compressed formats. cc: Juha-Pekka Heikkila cc: Bhanuprakash Modem cc: Swati Sharma Signed-off-by: Melanie Lobo --- lib/intel_aux_pgtable.c | 5 +++++ tests/intel/kms_flip_scaled_crc.c | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index 7c79521344de..a612df407692 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -21,6 +21,7 @@ #define AUX_FORMAT_AYUV 0x09 #define AUX_FORMAT_ARGB_8B 0x0A #define AUX_FORMAT_NV12_21 0x0F +#define AUX_FORMAT_XRGB16161616_64B 0x10 struct pgtable_level_desc { int idx_shift; @@ -305,6 +306,10 @@ static uint64_t pgt_get_l1_flags(const struct intel_buf *buf, int surface_idx) entry.e.format = AUX_FORMAT_ARGB_8B; entry.e.depth = bpp_to_depth_val(32); break; + case 64: + entry.e.format = AUX_FORMAT_XRGB16161616_64B; + entry.e.depth = bpp_to_depth_val(64); + break; default: igt_assert(0); } diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c index 2997b63fac40..6874f747b280 100644 --- a/tests/intel/kms_flip_scaled_crc.c +++ b/tests/intel/kms_flip_scaled_crc.c @@ -142,6 +142,14 @@ * Mega feature: General Display Features * Test category: functionality test * + * SUBTEST: flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-%s + * Description: Flip from 64bpp non scaled fb to 32bpp %arg[1] fb to stress CD + * clock programming + * Driver requirement: i915, xe + * Functionality: ccs, scaling, tiling, vblank + * Mega feature: General Display Features + * Test category: functionality test + * * arg[1]: * * @downscaling: Downscaled @@ -406,6 +414,14 @@ const struct { 1.0, 2.0, }, + { + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-downscaling", + "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming", + I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F, + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F, + 1.0, + 2.0, + }, { "flip-32bpp-ytile-to-64bpp-ytile-upscaling", "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming", @@ -590,6 +606,14 @@ const struct { 0.5, 1.0, }, + { + "flip-64bpp-4tile-to-32bpp-4tilemtlrcccs-upscaling", + "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming", + I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F, + I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F, + 0.5, + 1.0, + }, }; static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width, -- 2.17.1