From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Subject: [PATCH i-g-t 04/18] lib/xe/oa: Generate LNL metrics/registers files
Date: Fri, 16 Feb 2024 15:16:49 -0800 [thread overview]
Message-ID: <20240216231703.845644-5-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20240216231703.845644-1-ashutosh.dixit@intel.com>
Add LNL OA formats and generate metrics/registers .c and .h files with the
XE_OA_FORMAT_PEC64u64 format (called 576B_PEC64LL) used in
MetricsXML_P31.xml.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
lib/xe/oa-configs/oa-metricset-codegen.py | 53 +++++++++++++++++++++--
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/lib/xe/oa-configs/oa-metricset-codegen.py b/lib/xe/oa-configs/oa-metricset-codegen.py
index be9483af02f7..3c4e870701d6 100644
--- a/lib/xe/oa-configs/oa-metricset-codegen.py
+++ b/lib/xe/oa-configs/oa-metricset-codegen.py
@@ -81,6 +81,40 @@ def generate_metric_sets(args, gen):
#include <stdbool.h>
#include <assert.h>
+enum xe_oa_format_name {
+ XE_OA_FORMAT_C4_B8 = 1,
+
+ /* Gen8+ */
+ XE_OA_FORMAT_A12,
+ XE_OA_FORMAT_A12_B8_C8,
+ XE_OA_FORMAT_A32u40_A4u32_B8_C8,
+
+ /* DG2 */
+ XE_OAR_FORMAT_A32u40_A4u32_B8_C8,
+ XE_OA_FORMAT_A24u40_A14u32_B8_C8,
+
+ /* DG2/MTL OAC */
+ XE_OAC_FORMAT_A24u64_B8_C8,
+ XE_OAC_FORMAT_A22u32_R2u32_B8_C8,
+
+ /* MTL OAM */
+ XE_OAM_FORMAT_MPEC8u64_B8_C8,
+ XE_OAM_FORMAT_MPEC8u32_B8_C8,
+
+ /* Xe2+ */
+ XE_OA_FORMAT_PEC64u64,
+ XE_OA_FORMAT_PEC64u64_B8_C8,
+ XE_OA_FORMAT_PEC64u32,
+ XE_OA_FORMAT_PEC32u64_G1,
+ XE_OA_FORMAT_PEC32u32_G1,
+ XE_OA_FORMAT_PEC32u64_G2,
+ XE_OA_FORMAT_PEC32u32_G2,
+ XE_OA_FORMAT_PEC36u64_G1_32_G2_4,
+ XE_OA_FORMAT_PEC36u64_G1_4_G2_32,
+
+ XE_OA_FORMAT_MAX,
+};
+
"""))
c("#include \"{0}\"".format(os.path.basename(args.header)))
@@ -116,7 +150,7 @@ def generate_metric_sets(args, gen):
if gen.chipset.startswith("acm") or gen.chipset.startswith("mtl"):
if set.oa_format == "128B_MPEC8_NOA16":
c(textwrap.dedent("""\
- metric_set->perf_oa_format = I915_OAM_FORMAT_MPEC8u32_B8_C8;
+ metric_set->perf_oa_format = XE_OAM_FORMAT_MPEC8u32_B8_C8;
metric_set->perf_raw_size = 128;
metric_set->gpu_time_offset = 0;
@@ -128,7 +162,7 @@ def generate_metric_sets(args, gen):
"""))
else:
c(textwrap.dedent("""\
- metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;
+ metric_set->perf_oa_format = XE_OA_FORMAT_A24u40_A14u32_B8_C8;
metric_set->perf_raw_size = 256;
metric_set->gpu_time_offset = 0;
@@ -138,9 +172,22 @@ def generate_metric_sets(args, gen):
metric_set->c_offset = metric_set->b_offset + 8;
metric_set->perfcnt_offset = metric_set->c_offset + 8;
"""))
+ elif gen.chipset == "lnl":
+ c(textwrap.dedent("""\
+ metric_set->perf_oa_format = XE_OA_FORMAT_PEC64u64;
+
+ metric_set->perf_raw_size = 576;
+ metric_set->gpu_time_offset = 0;
+ metric_set->gpu_clock_offset = 1;
+ metric_set->a_offset = 2;
+ // metric_set->b_offset = metric_set->a_offset + 38;
+ // metric_set->c_offset = metric_set->b_offset + 8;
+ metric_set->perfcnt_offset = metric_set->a_offset + 64;
+
+ """))
else:
c(textwrap.dedent("""\
- metric_set->perf_oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
+ metric_set->perf_oa_format = XE_OA_FORMAT_A32u40_A4u32_B8_C8;
metric_set->perf_raw_size = 256;
metric_set->gpu_time_offset = 0;
--
2.41.0
next prev parent reply other threads:[~2024-02-16 23:17 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 23:16 [PATCH i-g-t 00/18] Intel Xe OA IGT's Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 01/18] lib/xe/oa: Import OA metric generation files from i915 Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 02/18] lib/xe/oa: Add LNL metric guids Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 03/18] lib/xe/oa: Add OA LNL metrics (oa_lnl.xml) Ashutosh Dixit
2024-02-16 23:16 ` Ashutosh Dixit [this message]
2024-02-16 23:16 ` [PATCH i-g-t 05/18] drm-uapi/xe: Sync with Perf/OA changes Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 06/18] lib/xe: Complete xe_oa lib changes Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 07/18] tests/intel/xe_query: Add OA units query test Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 08/18] tests/intel/xe_oa: Add first tests Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 09/18] tests/intel/xe_oa: Add some negative tests Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 10/18] tests/intel/xe_oa: Add "oa-formats" subtest Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 11/18] tests/intel/xe_oa: Add oa exponent tests Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 12/18] tests/intel/xe_oa: buffer-fill, non-zero-reason, enable-disable Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 13/18] tests/intel/xe_oa: blocking and polling tests Ashutosh Dixit
2024-02-16 23:16 ` [PATCH i-g-t 14/18] tests/intel/xe_oa: OAR/OAC tests Ashutosh Dixit
2024-02-16 23:17 ` [PATCH i-g-t 15/18] tests/intel/xe_oa: Exclusive/concurrent access, rc6 and stress open close Ashutosh Dixit
2024-02-16 23:17 ` [PATCH i-g-t 16/18] tests/intel/xe_oa: add remove OA config tests Ashutosh Dixit
2024-02-16 23:17 ` [PATCH i-g-t 17/18] tests/intel/xe_oa: OA buffer mmap tests Ashutosh Dixit
2024-02-16 23:17 ` [PATCH i-g-t 18/18] tests/intel/xe_oa: Register whitelisting and MMIO trigger tests Ashutosh Dixit
2024-02-16 23:39 ` ✗ GitLab.Pipeline: warning for Intel Xe OA IGT's Patchwork
2024-02-17 0:11 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-17 0:12 ` ✗ CI.xeBAT: failure " Patchwork
2024-02-17 17:10 ` ✗ Fi.CI.IGT: " Patchwork
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