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From: sai.gowtham.ch@intel.com
To: igt-dev@lists.freedesktop.org, zbigniew.kempczynski@intel.com,
	sai.gowtham.ch@intel.com
Subject: [PATCH i-g-t 2/3] lib/xe/xe_spin: Add support to store/write ctx time
Date: Wed, 20 Mar 2024 21:24:29 +0530	[thread overview]
Message-ID: <20240320155430.11877-3-sai.gowtham.ch@intel.com> (raw)
In-Reply-To: <20240320155430.11877-1-sai.gowtham.ch@intel.com>

From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>

support to Store or write ctx time stamps when a spinner is
triggers, which makes user to understand if spinner is still
submitting workload to a context.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
 lib/xe/xe_spin.c | 12 ++++++++++++
 lib/xe/xe_spin.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 1ca54ea19..2c9b5848a 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -72,6 +72,7 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 	uint64_t end_addr = opts->addr + offsetof(struct xe_spin, end);
 	uint64_t ticks_delta_addr = opts->addr + offsetof(struct xe_spin, ticks_delta);
 	uint64_t pad_addr = opts->addr + offsetof(struct xe_spin, pad);
+	uint64_t timestamp_addr = opts->addr + offsetof(struct xe_spin, timestamp);
 	int b = 0;
 
 	spin->start = 0;
@@ -98,6 +99,17 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 	if (opts->preempt)
 		spin->batch[b++] = (0x5 << 23);
 
+	if (opts->write_timestamp) {
+		spin->batch[b++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO | MI_LRR_SRC_CS_MMIO;
+		spin->batch[b++] = CTX_TIMESTAMP;
+		spin->batch[b++] = CS_GPR(NOW_TS);
+
+		spin->batch[b++] = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_CS_MMIO;
+		spin->batch[b++] = CS_GPR(NOW_TS);
+		spin->batch[b++] = timestamp_addr;
+		spin->batch[b++] = timestamp_addr >> 32;
+	}
+
 	if (opts->ctx_ticks) {
 		spin->batch[b++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_CS_MMIO;
 		spin->batch[b++] = CS_GPR(NOW_TS) + 4;
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 87b7c1716..d65adb05c 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -29,6 +29,7 @@ struct xe_spin_opts {
 	uint64_t addr;
 	bool preempt;
 	uint32_t ctx_ticks;
+	bool write_timestamp;
 };
 
 /* Mapped GPU object */
@@ -39,6 +40,7 @@ struct xe_spin {
 	uint32_t end;
 	uint32_t ticks_delta;
 	uint64_t exec_sync;
+	uint32_t timestamp;
 };
 
 igt_spin_t *xe_spin_create(int fd, const struct igt_spin_factory *opt);
-- 
2.39.1


  parent reply	other threads:[~2024-03-20 15:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-20 15:54 [PATCH i-g-t 0/3] tests/intel/xe_exec_compute_mode: Test to sai.gowtham.ch
2024-03-20 15:54 ` [PATCH i-g-t 1/3] lib/xe/xe_spin: Update xe_spin with exec_sync sai.gowtham.ch
2024-03-21  9:53   ` Zbigniew Kempczyński
2024-03-20 15:54 ` sai.gowtham.ch [this message]
2024-03-21  9:57   ` [PATCH i-g-t 2/3] lib/xe/xe_spin: Add support to store/write ctx time Zbigniew Kempczyński
2024-03-20 15:54 ` [PATCH i-g-t 3/3] tests/intel/xe_exec_compute_mode: Test to validate LR mode sai.gowtham.ch
2024-03-21 10:06   ` Zbigniew Kempczyński
2024-03-20 17:20 ` ✓ CI.xeBAT: success for tests/intel/xe_exec_compute_mode: Test to (rev2) Patchwork
2024-03-20 17:32 ` ✓ Fi.CI.BAT: " Patchwork
2024-03-21  7:10 ` ✗ Fi.CI.IGT: failure " Patchwork

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