From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BFA1C6FD1F for ; Thu, 21 Mar 2024 18:42:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD7CD10FD64; Thu, 21 Mar 2024 18:42:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QphVhEnR"; dkim-atps=neutral Received: from mail-yw1-f182.google.com (mail-yw1-f182.google.com [209.85.128.182]) by gabe.freedesktop.org (Postfix) with ESMTPS id 170BC10FD64 for ; Thu, 21 Mar 2024 18:42:08 +0000 (UTC) Received: by mail-yw1-f182.google.com with SMTP id 00721157ae682-60cbcd04de9so13188747b3.2 for ; Thu, 21 Mar 2024 11:42:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711046527; x=1711651327; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CTOWc5u1+H9+LFabx4a6z2ntm/zRz7juckKAPz7Vjtg=; b=QphVhEnR0/OjvcIaFKJX1Coba1c/9AfSg6IZ4SB1aM3/rYETYIAOdOfUFYeAff/aXo aEnZ7LfnFNtMsgPir9cEqDN7yzeEeJDhsocDIfuMNiX5t7tvRXueBa/M9XRozObrkwDj QEWoYL5QRkCp7hcIf9fqTxtbNma4aF7dY8D3LtatE0WA/YNBwnhwJSejr7HgcHuaVEid WH9Tgxy3TR7XzEAxlbjXnCTISc6RESh5QANIKY7z7h6ezYxTR49/PbaPqX/RbpGYU6ai uFxfYQDRRClOW9eGT765ZPeaftO2Ndz9mIsZmnStPa4DMelad2wyJ3w82p6/MnMMLzcX EEJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711046527; x=1711651327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CTOWc5u1+H9+LFabx4a6z2ntm/zRz7juckKAPz7Vjtg=; b=xNsYQ56zE987YFu+Svc/0MgZIfjWht89qpm8bxXpUY3InXjKEARsFVN6dHJaaqAbfA bgakcZpvt2vYPMYOb8h5RVDne8QB+NoDvhu0cOe05CUrrYqa1oKy0jZOjpgkKNDxtz4U vBFWxFdHlGS0GZSWqpQ5qJvObu4TzCmS5Ed5rNbP5IdX0UReRFDKoWZRLng7p6+pWz36 sY0bgooEjFNp2AsQ74maDA5XdxMbmh8FleaTRfyBOJKp2rZfOziStWmGLPBjJOvlEXR6 zTgcl06lFyO64tiEs0FYXV4eihV9wLWEvdcC4r/58hpMJ5ywdsqEUWleGlJj4gKs9gLU iZSg== X-Gm-Message-State: AOJu0YxRd5bA9dMTeSIZR23jQzKil1e5kZGj2mrtcWxoGOPd5gbYbExu /EjKlvQTkvBXi0Q8Wpysmz1E7ZTpTyMYwh8VgN1UTr2wc07ibzq91DSkldaN X-Google-Smtp-Source: AGHT+IH6Tn8+SfzewWUCD9HuhClA+iftVFVfIUe7cYQUhCIFLHUEbbNy3vqJzosh24pkI/ls6UhT6Q== X-Received: by 2002:a81:6f55:0:b0:611:16f0:51b9 with SMTP id k82-20020a816f55000000b0061116f051b9mr93265ywc.15.1711046526708; Thu, 21 Mar 2024 11:42:06 -0700 (PDT) Received: from localhost ([162.208.5.36]) by smtp.gmail.com with ESMTPSA id o11-20020a0dcc0b000000b0060cb9691f78sm47929ywd.52.2024.03.21.11.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 11:42:05 -0700 (PDT) From: Matt Turner To: igt-dev@lists.freedesktop.org Cc: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= , Kamil Konieczny , Matt Turner Subject: [PATCH v2] lib: Inline igt_x86_features() into ifunc resolvers Date: Thu, 21 Mar 2024 14:41:50 -0400 Message-ID: <20240321184150.26552-1-mattst88@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240304221800.1161896-1-mattst88@gmail.com> References: <20240304221800.1161896-1-mattst88@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Quoting https://sourceware.org/glibc/wiki/GNU_IFUNC > When LD_BIND_NOW=1 or -Wl,z,now is in effect symbols must be > immediately resolved at startup. In cases where an external function > call depends needs to be made that may fail if such a call has not > been initialized yet (PLT-based relocation which is processed later). > For example calling strlen in an IFUNC resolver built with -Wl,z,now > may lead to a segfault because the PLT is not yet resolved. We cannot rely on function calls through the PLT in ifunc resolvers as the PLT may not have been initialized yet. In practice, this causes crashes when igt is linked with -Wl,-z,now or when linked with the mold linker. To avoid this problem, we do two things: 1. move igt_x86_features() to igt_x86.h so its definition is available to compilation units that call the function. 2. mark the ifunc resolvers with __attribute__((flatten)) to ensure igt_x86_features() is inlined. Since this function is only called from a few places it does not significantly increase binary size to inline it. Linux distros (at least Fedora since v23, Gentoo/Hardened, soon standard Gentoo) use `-Wl,-z now` to improve security. By binding upfront, the loader can mark the GOT as read-only for a security enhancement. See https://wiki.gentoo.org/wiki/Hardened/Toolchain for more details. Bug: https://bugs.gentoo.org/788625 Bug: https://bugs.gentoo.org/925348 Reviewed-by: Zbigniew Kempczyński Signed-off-by: Matt Turner --- lib/igt_halffloat.c | 8 +++ lib/igt_x86.c | 119 ++------------------------------------------ lib/igt_x86.h | 117 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 128 insertions(+), 116 deletions(-) diff --git a/lib/igt_halffloat.c b/lib/igt_halffloat.c index 5dbe08e01..560952d20 100644 --- a/lib/igt_halffloat.c +++ b/lib/igt_halffloat.c @@ -194,6 +194,10 @@ static void half_to_float(const uint16_t *h, float *f, unsigned int num) f[i] = _half_to_float(h[i]); } +/* The PLT is not initialized when ifunc resolvers run, so all external + * functions must be inlined with __attribute__((flatten)). + */ +__attribute__((flatten)) static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned int num) { if (igt_x86_features() & F16C) @@ -205,6 +209,10 @@ static void (*resolve_float_to_half(void))(const float *f, uint16_t *h, unsigned void igt_float_to_half(const float *f, uint16_t *h, unsigned int num) __attribute__((ifunc("resolve_float_to_half"))); +/* The PLT is not initialized when ifunc resolvers run, so all external + * functions must be inlined with __attribute__((flatten)). + */ +__attribute__((flatten)) static void (*resolve_half_to_float(void))(const uint16_t *h, float *f, unsigned int num) { if (igt_x86_features() & F16C) diff --git a/lib/igt_x86.c b/lib/igt_x86.c index 8c102fd13..f60568be5 100644 --- a/lib/igt_x86.c +++ b/lib/igt_x86.c @@ -27,14 +27,6 @@ #include "config.h" -#ifdef HAVE_CPUID_H -#include -#else -#define __get_cpuid_max(x, y) 0 -#define __cpuid(level, a, b, c, d) a = b = c = d = 0 -#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0 -#endif - #include "igt_x86.h" #include "igt_aux.h" @@ -49,114 +41,7 @@ * @include: igt_x86.h */ -#define BASIC_CPUID 0x0 -#define EXTENDED_CPUID 0x80000000 - -#ifndef bit_MMX -#define bit_MMX (1 << 23) -#endif - -#ifndef bit_SSE -#define bit_SSE (1 << 25) -#endif - -#ifndef bit_SSE2 -#define bit_SSE2 (1 << 26) -#endif - -#ifndef bit_SSE3 -#define bit_SSE3 (1 << 0) -#endif - -#ifndef bit_SSSE3 -#define bit_SSSE3 (1 << 9) -#endif - -#ifndef bit_SSE4_1 -#define bit_SSE4_1 (1 << 19) -#endif - -#ifndef bit_SSE4_2 -#define bit_SSE4_2 (1 << 20) -#endif - -#ifndef bit_OSXSAVE -#define bit_OSXSAVE (1 << 27) -#endif - -#ifndef bit_AVX -#define bit_AVX (1 << 28) -#endif - -#ifndef bit_F16C -#define bit_F16C (1 << 29) -#endif - -#ifndef bit_AVX2 -#define bit_AVX2 (1<<5) -#endif - -#define xgetbv(index,eax,edx) \ - __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index)) - -#define has_YMM 0x1 - #if defined(__x86_64__) || defined(__i386__) -unsigned igt_x86_features(void) -{ - unsigned max = __get_cpuid_max(BASIC_CPUID, 0); - unsigned eax, ebx, ecx, edx; - unsigned features = 0; - unsigned extra = 0; - - if (max >= 1) { - __cpuid(1, eax, ebx, ecx, edx); - - if (ecx & bit_SSE3) - features |= SSE3; - - if (ecx & bit_SSSE3) - features |= SSSE3; - - if (ecx & bit_SSE4_1) - features |= SSE4_1; - - if (ecx & bit_SSE4_2) - features |= SSE4_2; - - if (ecx & bit_OSXSAVE) { - unsigned int bv_eax, bv_ecx; - xgetbv(0, bv_eax, bv_ecx); - if ((bv_eax & 6) == 6) - extra |= has_YMM; - } - - if ((extra & has_YMM) && (ecx & bit_AVX)) - features |= AVX; - - if (edx & bit_MMX) - features |= MMX; - - if (edx & bit_SSE) - features |= SSE; - - if (edx & bit_SSE2) - features |= SSE2; - - if (ecx & bit_F16C) - features |= F16C; - } - - if (max >= 7) { - __cpuid_count(7, 0, eax, ebx, ecx, edx); - - if ((extra & has_YMM) && (ebx & bit_AVX2)) - features |= AVX2; - } - - return features; -} - char *igt_x86_features_to_string(unsigned features, char *line) { char *ret = line; @@ -284,6 +169,10 @@ static void memcpy_from_wc(void *dst, const void *src, unsigned long len) memcpy(dst, src, len); } +/* The PLT is not initialized when ifunc resolvers run, so all external + * functions must be inlined with __attribute__((flatten)). + */ +__attribute__((flatten)) static void (*resolve_memcpy_from_wc(void))(void *, const void *, unsigned long) { if (igt_x86_features() & SSE4_1) diff --git a/lib/igt_x86.h b/lib/igt_x86.h index c7b84dec2..1e0195c4b 100644 --- a/lib/igt_x86.h +++ b/lib/igt_x86.h @@ -30,6 +30,14 @@ #ifndef IGT_X86_H #define IGT_X86_H +#ifdef HAVE_CPUID_H +#include +#else +#define __get_cpuid_max(x, y) 0 +#define __cpuid(level, a, b, c, d) a = b = c = d = 0 +#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0 +#endif + #define MMX 0x1 #define SSE 0x2 #define SSE2 0x4 @@ -42,7 +50,114 @@ #define F16C 0x200 #if defined(__x86_64__) || defined(__i386__) -unsigned igt_x86_features(void); + +#define BASIC_CPUID 0x0 +#define EXTENDED_CPUID 0x80000000 + +#ifndef bit_MMX +#define bit_MMX (1 << 23) +#endif + +#ifndef bit_SSE +#define bit_SSE (1 << 25) +#endif + +#ifndef bit_SSE2 +#define bit_SSE2 (1 << 26) +#endif + +#ifndef bit_SSE3 +#define bit_SSE3 (1 << 0) +#endif + +#ifndef bit_SSSE3 +#define bit_SSSE3 (1 << 9) +#endif + +#ifndef bit_SSE4_1 +#define bit_SSE4_1 (1 << 19) +#endif + +#ifndef bit_SSE4_2 +#define bit_SSE4_2 (1 << 20) +#endif + +#ifndef bit_OSXSAVE +#define bit_OSXSAVE (1 << 27) +#endif + +#ifndef bit_AVX +#define bit_AVX (1 << 28) +#endif + +#ifndef bit_F16C +#define bit_F16C (1 << 29) +#endif + +#ifndef bit_AVX2 +#define bit_AVX2 (1<<5) +#endif + +#define xgetbv(index,eax,edx) \ + __asm__ ("xgetbv" : "=a"(eax), "=d"(edx) : "c" (index)) + +#define has_YMM 0x1 + +static inline unsigned igt_x86_features(void) +{ + unsigned max = __get_cpuid_max(BASIC_CPUID, 0); + unsigned eax, ebx, ecx, edx; + unsigned features = 0; + unsigned extra = 0; + + if (max >= 1) { + __cpuid(1, eax, ebx, ecx, edx); + + if (ecx & bit_SSE3) + features |= SSE3; + + if (ecx & bit_SSSE3) + features |= SSSE3; + + if (ecx & bit_SSE4_1) + features |= SSE4_1; + + if (ecx & bit_SSE4_2) + features |= SSE4_2; + + if (ecx & bit_OSXSAVE) { + unsigned int bv_eax, bv_ecx; + xgetbv(0, bv_eax, bv_ecx); + if ((bv_eax & 6) == 6) + extra |= has_YMM; + } + + if ((extra & has_YMM) && (ecx & bit_AVX)) + features |= AVX; + + if (edx & bit_MMX) + features |= MMX; + + if (edx & bit_SSE) + features |= SSE; + + if (edx & bit_SSE2) + features |= SSE2; + + if (ecx & bit_F16C) + features |= F16C; + } + + if (max >= 7) { + __cpuid_count(7, 0, eax, ebx, ecx, edx); + + if ((extra & has_YMM) && (ebx & bit_AVX2)) + features |= AVX2; + } + + return features; +} + char *igt_x86_features_to_string(unsigned features, char *line); #else static inline unsigned igt_x86_features(void) -- 2.43.2