From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA883C10F1A for ; Thu, 9 May 2024 05:34:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A1EF10E191; Thu, 9 May 2024 05:34:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Y6HJu/3m"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB97D10E191 for ; Thu, 9 May 2024 05:34:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715232873; x=1746768873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RrhzmVqtg87Pftb+qGn4QjIykLUUPa8A4BlahOYJYFo=; b=Y6HJu/3me9bQFljCLlviyw71OWs7/YWP6ixbviKbBwHK3UjdFMJ1zgs1 h8h56Ck1+1JUDX5bLWy7PHjIrQdWgHZZTiz+/ghc+lS11YoTKI6gQr6Jb 42OjSrDvvP9ddCxABRSGQrCYnxBMV+LV1eKIieHWv5o2Yc9UWBFZkKr4u 6N4buL8JvGB7/OSr8MSVDftawxquC4XuEgu8qG6GkOzFKsnkN35/HOOm9 P7qoFKj9sIHpEnHPCgyK2YH98H8Og7oO5rqXl+IPFxyF1Q0XaPhOJMDiS TuuH24hgD+7sY/JTdBrxn2ubMeEh4N9a+I+3VZSlBxvqheZIEipLKLEZQ Q==; X-CSE-ConnectionGUID: QF5B+tXCS9agPeeiDIUamA== X-CSE-MsgGUID: IJemrhF3R5CXTPyz4JROqg== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="21802925" X-IronPort-AV: E=Sophos;i="6.08,146,1712646000"; d="scan'208";a="21802925" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2024 22:34:33 -0700 X-CSE-ConnectionGUID: xGwYVzcTTqORNN/1IX5zXQ== X-CSE-MsgGUID: XWqlVtTtQi2+qJzVG7YIiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,146,1712646000"; d="scan'208";a="29187254" Received: from unknown (HELO localhost) ([10.245.246.122]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2024 22:34:32 -0700 From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Cc: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= , Juha-Pekka Heikkila Subject: [PATCH i-g-t v5 06/11] lib/rendercopy_gen9: Separate xe and xe2 compression format Date: Thu, 9 May 2024 07:33:54 +0200 Message-Id: <20240509053359.449885-7-zbigniew.kempczynski@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240509053359.449885-1-zbigniew.kempczynski@intel.com> References: <20240509053359.449885-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Xe and beyond differ how compression format is handled. For Xe it is 5-bit long whereas for Xe2+ this is 4-bit long field. Instead of artifically packing 0-15 into 5-bit field lets separate this structures to conform with the documentation. Signed-off-by: Zbigniew Kempczyński Cc: Juha-Pekka Heikkila --- lib/gen9_render.h | 31 +++++++++++++++++++++---------- lib/rendercopy_gen9.c | 24 ++++++++++++++++-------- 2 files changed, 37 insertions(+), 18 deletions(-) diff --git a/lib/gen9_render.h b/lib/gen9_render.h index 8ed60a2a54..4c1ed4726a 100644 --- a/lib/gen9_render.h +++ b/lib/gen9_render.h @@ -154,16 +154,27 @@ struct gen9_surface_state { uint32_t aux_base_addr_hi; } ss11; - struct { - /* - * compression_format is used only dg2 onward. - * prior to dg2 full ss12 is used for the address - * but due to alignments bits 0..6 will be zero - * and asserted in code to be so - */ - uint32_t compression_format:5; - uint32_t pad0:1; - uint32_t clear_address:26; + union { + struct { + /* + * compression_format is used only dg2 onward. + * prior to dg2 full ss12 is used for the address + * but due to alignments bits 0..6 will be zero + * and asserted in code to be so + */ + uint32_t compression_format:5; + uint32_t pad0:1; + uint32_t clear_address:26; + } xe; + + struct { + /* + * On Xe2+ compression format is 4-bit long. + */ + uint32_t compression_format:4; + uint32_t mip_region_depth_in_log:4; + uint32_t pad0:24; + } xe2; } ss12; struct { diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 7c7563d50c..35d79acbab 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -264,7 +264,7 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, igt_assert(__builtin_ctzl(address + buf->cc.offset) >= 6 && (__builtin_clzl(address + buf->cc.offset) >= 16)); - ss->ss12.clear_address = (address + buf->cc.offset) >> 6; + ss->ss12.xe.clear_address = (address + buf->cc.offset) >> 6; ss->ss13.clear_address_hi = (address + buf->cc.offset) >> 32; } @@ -274,13 +274,21 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, ss->ss7.dg2.disable_support_for_multi_gpu_partial_writes = 1; ss->ss7.dg2.disable_support_for_multi_gpu_atomics = 1; - /* - * For now here is coming only 32bpp rgb format - * which is marked below as B8G8R8X8_UNORM = '8' - * If here ever arrive other formats below need to be - * fixed to take that into account. - */ - ss->ss12.compression_format = 8; + if (AT_LEAST_GEN(ibb->devid, 20)) { + /* + * For Xe2+ R8G8B8A8 best compression ratio is + * achieved with compression format = '2' + */ + ss->ss12.xe2.compression_format = 2; + } else { + /* + * For now here is coming only 32bpp rgb format + * which is marked below as B8G8R8X8_UNORM = '8' + * If here ever arrive other formats below need to be + * fixed to take that into account. + */ + ss->ss12.xe.compression_format = 8; + } } } -- 2.34.1