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d="scan'208";a="30428040" Received: from bommu-optiplex-5060.iind.intel.com ([10.145.169.63]) by orviesa010.jf.intel.com with ESMTP; 14 May 2024 00:10:18 -0700 From: Bommu Krishnaiah To: igt-dev@lists.freedesktop.org Cc: Bommu Krishnaiah , Oak Zeng , Himal Prasad Ghimiray Subject: [PATCH i-g-t v2 10/10] tests/intel/xe_svm: svm-sparse-access Date: Tue, 14 May 2024 12:40:26 +0530 Message-Id: <20240514071026.748257-11-krishnaiah.bommu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240514071026.748257-1-krishnaiah.bommu@intel.com> References: <20240514071026.748257-1-krishnaiah.bommu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Verify Sparsely access two memory locations with svm Signed-off-by: Bommu Krishnaiah Cc: Oak Zeng Cc: Himal Prasad Ghimiray --- lib/xe/xe_util.c | 15 +++++++++++++++ lib/xe/xe_util.h | 1 + tests/intel/xe_svm.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c index a02ee5324..fc07c14b7 100644 --- a/lib/xe/xe_util.c +++ b/lib/xe/xe_util.c @@ -142,6 +142,21 @@ void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val *batch++ = MI_BATCH_BUFFER_END; } +void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val) +{ + int i = 0; + + batch[i] = MI_STORE_DWORD_IMM; + batch[++i] = dst_va; + batch[++i] = dst_va >> 32; + batch[++i] = val; + batch[++i] = MI_STORE_DWORD_IMM; + batch[++i] = dst_va1; + batch[++i] = dst_va1 >> 32; + batch[++i] = val; + batch[++i] = MI_BATCH_BUFFER_END; +} + void xe_create_cmdbuf(struct xe_buffer *cmd_buf, cmdbuf_fill_func_t fill_func, uint64_t dst_va, uint32_t val, struct drm_xe_engine_class_instance *eci) { //make some room for a exec_ufence, which will be used to sync the diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h index 50f2a4bc4..f463cca3b 100644 --- a/lib/xe/xe_util.h +++ b/lib/xe/xe_util.h @@ -46,6 +46,7 @@ uint64_t *xe_cmdbuf_exec_ufence_cpuva(struct xe_buffer *cmd_buf); void insert_store(uint32_t *batch, uint64_t dst_va, uint32_t val); void insert_atomic_inc(uint32_t *batch, uint64_t dst_va, uint32_t val); void insert_memset(uint32_t *batch, uint64_t dst_va, uint64_t size, uint32_t val); +void insert_two_stores(uint32_t *batch, uint64_t dst_va, uint64_t dst_va1, uint32_t val); void xe_submit_cmd(struct xe_buffer *cmdbuf); int64_t __xe_submit_cmd(struct xe_buffer *cmdbuf); void xe_destroy_buffer(struct xe_buffer *buffer); diff --git a/tests/intel/xe_svm.c b/tests/intel/xe_svm.c index e8989afaa..fbda6aaea 100644 --- a/tests/intel/xe_svm.c +++ b/tests/intel/xe_svm.c @@ -38,6 +38,8 @@ * Description: verify SVM functionality while accessing read only memory * SUBTEST: svm-benchmark * Description: verify SVM performance with simple benchmark test + * SUBTEST: svm-sparse-access + * Description: verify Sparsely access two memory locations with svm */ #include @@ -330,6 +332,39 @@ static void svm_benchmark(int fd, uint32_t vm, struct drm_xe_engine_class_instan igt_info("engine class %d, engine id %d memset E2E bandwidth(include sync overhead) %.3f MiB/s\n", eci->engine_class, eci->engine_instance, bandwidth); } +/** + * Sparsely access two memory locations + */ +static void svm_sparse_access(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci) +{ + uint64_t gpu_va = 0x1a0000; + size_t bo_size = xe_bb_size(fd, PAGE_ALIGN_UFENCE); + uint32_t size = 1024*1024, sz_dw = size/4; + uint32_t *dst, *dst_to_access, *dst_to_access1; + + struct xe_buffer cmd_buf = { + .fd = fd, + .gpu_addr = (void *)(uintptr_t)gpu_va, + .vm = vm, + .size = bo_size, + .placement = vram_if_possible(fd, eci->gt_id), + .flag = DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM, + }; + + dst = malloc(size); + dst_to_access = dst + (sz_dw>>1); + dst_to_access1 = dst + (sz_dw>>2); + + xe_create_cmdbuf_fill_two_dw(&cmd_buf, insert_two_stores, (uint64_t)dst_to_access, (uint64_t)dst_to_access1, 0xc0ffee, eci); + xe_submit_cmd(&cmd_buf); + + igt_assert_eq(*dst_to_access, 0xc0ffee); + igt_assert_eq(*dst_to_access1, 0xc0ffee); + + xe_destroy_cmdbuf(&cmd_buf); + free(dst); +} + igt_main { int fd; @@ -380,6 +415,10 @@ igt_main xe_for_each_engine(fd, hwe) svm_benchmark(fd, vm, hwe); + igt_subtest_f("svm-sparse-access") + xe_for_each_engine(fd, hwe) + svm_sparse_access(fd, vm, hwe); + igt_fixture { xe_vm_destroy(fd, vm); drm_close_driver(fd); -- 2.25.1