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([10.245.245.127]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 01:04:32 -0700 From: Vinod Govindapillai To: igt-dev@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, juha-pekka.heikkila@intel.com, jouni.hogander@intel.com, jonathan.cavitt@intel.com Subject: [PATCH i-g-t v3 2/5] lib/i915/fbc: add fbc frame size check helper functions Date: Tue, 11 Jun 2024 11:04:13 +0300 Message-Id: <20240611080416.56878-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240611080416.56878-1-vinod.govindapillai@intel.com> References: <20240611080416.56878-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Add helper functions to check maximum plane size fbc can be supported in a display version. v2: Add function to get max plane size for FBC (Jonathan Cavitt) Reviewed-by: Jonathan Cavitt #v1 Signed-off-by: Vinod Govindapillai --- lib/i915/intel_fbc.c | 55 ++++++++++++++++++++++++++++++++++++++++++++ lib/i915/intel_fbc.h | 2 ++ 2 files changed, 57 insertions(+) diff --git a/lib/i915/intel_fbc.c b/lib/i915/intel_fbc.c index 07ed7f469..2096bd996 100644 --- a/lib/i915/intel_fbc.c +++ b/lib/i915/intel_fbc.c @@ -99,3 +99,58 @@ bool intel_fbc_wait_until_enabled(int device, enum pipe pipe) return enabled; } + +/** + * intel_fbc_max_plane_size + * + * @fd: fd of the device + * @width: To get the max supported width + * @height: To get the max supported height + * + * Function to update maximum plane size supported by FBC per platform + * + * Returns: + * None + */ +void intel_fbc_max_plane_size(int fd, uint32_t *width, uint32_t *height) +{ + const uint32_t dev_id = intel_get_drm_devid(fd); + const struct intel_device_info *info = intel_get_device_info(dev_id); + int ver = info->graphics_ver; + + if (ver >= 10) { + *width = 5120; + *height = 4096; + } else if (ver >= 8 || IS_HASWELL(fd)) { + *width = 4096; + *height = 4096; + } else if (IS_G4X(fd) || ver >= 5) { + *width = 4096; + *height = 2048; + } else { + *width = 2048; + *height = 1536; + } +} + + +/** + * intel_fbc_plane_size_supported + * + * @fd: fd of the device + * @width: width of the plane to be checked + * @height: height of the plane to be checked + * + * Checks if the plane size is supported for FBC + * + * Returns: + * true if plane size is within the range as per the FBC supported size restrictions per platform + */ +bool intel_fbc_plane_size_supported(int fd, uint32_t width, uint32_t height) +{ + unsigned int max_w, max_h; + + intel_fbc_max_plane_size(fd, &max_w, &max_h); + + return width <= max_w && height <= max_h; +} diff --git a/lib/i915/intel_fbc.h b/lib/i915/intel_fbc.h index 995dc7f1e..5cca5dfd9 100644 --- a/lib/i915/intel_fbc.h +++ b/lib/i915/intel_fbc.h @@ -14,5 +14,7 @@ bool intel_fbc_supported_on_chipset(int device, enum pipe pipe); bool intel_fbc_wait_until_enabled(int device, enum pipe pipe); bool intel_fbc_is_enabled(int device, enum pipe pipe, int log_level); +void intel_fbc_max_plane_size(int fd, uint32_t *width, uint32_t *height); +bool intel_fbc_plane_size_supported(int device, uint32_t width, uint32_t height); #endif -- 2.34.1