From: Matt Roper <matthew.d.roper@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: <igt-dev@lists.freedesktop.org>
Subject: Re: [PATCH i-g-t 2/2] tests/intel/xe_pat: account for Wa_16023588340
Date: Fri, 21 Jun 2024 13:40:54 -0700 [thread overview]
Message-ID: <20240621204054.GS2906448@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20240619143542.110461-2-matthew.auld@intel.com>
On Wed, Jun 19, 2024 at 03:35:42PM +0100, Matthew Auld wrote:
> We can't use the CLOS3 entries on BMG g21.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> tests/intel/xe_pat.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index fe6a367aa..82155f1d5 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -929,6 +929,18 @@ const struct pat_index_entry xe2_pat_index_modes[] = {
> { NULL, 31, false, "c3-2way", XE_COH_AT_LEAST_1WAY },
> };
>
> +const struct pat_index_entry bmg_g21_pat_index_modes[] = {
> + XE_COMMON_PAT_INDEX_MODES,
> +
> + /* Too many, just pick some of the interesting ones */
> + { NULL, 1, false, "1way", XE_COH_AT_LEAST_1WAY },
> + { NULL, 2, false, "2way", XE_COH_AT_LEAST_1WAY },
> + { NULL, 2, false, "2way-cpu-wc", XE_COH_AT_LEAST_1WAY, true },
> + { NULL, 5, false, "uc-1way", XE_COH_AT_LEAST_1WAY },
> + { NULL, 12, true, "uc-comp", XE_COH_NONE },
> + { NULL, 27, false, "c2-2way", XE_COH_AT_LEAST_1WAY },
> +};
> +
> /*
> * Depending on 2M/1G GTT pages we might trigger different PTE layouts for the
> * PAT bits, so make sure we test with and without huge-pages. Also ensure we
> @@ -1169,8 +1181,13 @@ igt_main_args("V", NULL, help_str, opt_handler, NULL)
> igt_subtest_with_dynamic("pat-index-xe2") {
> igt_require(intel_get_device_info(dev_id)->graphics_ver >= 20);
> igt_assert(HAS_FLATCCS(dev_id));
> - subtest_pat_index_modes_with_regions(fd, xe2_pat_index_modes,
> - ARRAY_SIZE(xe2_pat_index_modes));
> +
> + if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
> + subtest_pat_index_modes_with_regions(fd, bmg_g21_pat_index_modes,
> + ARRAY_SIZE(bmg_g21_pat_index_modes));
> + else
> + subtest_pat_index_modes_with_regions(fd, xe2_pat_index_modes,
> + ARRAY_SIZE(xe2_pat_index_modes));
> }
>
> igt_subtest("display-vs-wb-transient")
> --
> 2.45.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
next prev parent reply other threads:[~2024-06-21 20:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 14:35 [PATCH i-g-t 1/2] lib/intel_pat: account for Wa_16023588340 Matthew Auld
2024-06-19 14:35 ` [PATCH i-g-t 2/2] tests/intel/xe_pat: " Matthew Auld
2024-06-21 20:40 ` Matt Roper [this message]
2024-06-19 19:51 ` ✓ CI.xeBAT: success for series starting with [i-g-t,1/2] lib/intel_pat: " Patchwork
2024-06-19 20:00 ` ✓ Fi.CI.BAT: " Patchwork
2024-06-20 0:08 ` ✓ Fi.CI.IGT: " Patchwork
2024-06-20 3:31 ` ✗ CI.xeFULL: failure " Patchwork
2024-06-21 20:40 ` [PATCH i-g-t 1/2] " Matt Roper
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