From: Lucas De Marchi <lucas.demarchi@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH i-g-t v2] tests/intel/xe_query: Sanity check EU width
Date: Wed, 10 Jul 2024 14:59:56 -0700 [thread overview]
Message-ID: <20240710220050.2169596-1-lucas.demarchi@intel.com> (raw)
Add a sanity check for kernel returning the expected EU width in the
topology query.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
This depends on patch series to be submitted to the kernel. The local
defines are done to be able to test, but should be replaced by an update
to the uapi headers.
tests/intel/xe_query.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tests/intel/xe_query.c b/tests/intel/xe_query.c
index 92f82f6ee..361c30492 100644
--- a/tests/intel/xe_query.c
+++ b/tests/intel/xe_query.c
@@ -20,6 +20,8 @@
#include "xe/xe_query.h"
#include "intel_hwconfig_types.h"
+#define LOCAL_DRM_XE_TOPO_SIMD16_EU_PER_DSS 5
+
void dump_hex(void *buffer, int len);
void dump_hex_debug(void *buffer, int len);
const char *get_hwconfig_name(int param);
@@ -168,6 +170,7 @@ const char *get_topo_name(int value)
case DRM_XE_TOPO_DSS_COMPUTE: return "DSS_COMPUTE";
case DRM_XE_TOPO_EU_PER_DSS: return "EU_PER_DSS";
case DRM_XE_TOPO_L3_BANK: return "L3_BANK";
+ case LOCAL_DRM_XE_TOPO_SIMD16_EU_PER_DSS: return "SIMD16_EU_PER_DSS";
}
return "??";
}
@@ -354,6 +357,7 @@ test_query_gt_list(int fd)
static void
test_query_gt_topology(int fd)
{
+ uint16_t dev_id = intel_get_drm_devid(fd);
struct drm_xe_query_topology_mask *topology;
int pos = 0;
struct drm_xe_device_query query = {
@@ -362,6 +366,7 @@ test_query_gt_topology(int fd)
.size = 0,
.data = 0,
};
+ uint32_t topo_types = 0;
igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query), 0);
igt_assert_neq(query.size, 0);
@@ -378,15 +383,28 @@ test_query_gt_topology(int fd)
while (query.size >= sizeof(struct drm_xe_query_topology_mask)) {
struct drm_xe_query_topology_mask *topo = (struct drm_xe_query_topology_mask*)((unsigned char*)topology + pos);
int sz = sizeof(struct drm_xe_query_topology_mask) + topo->num_bytes;
+
igt_info(" gt_id: %2d type: %-12s (%d) n:%d [%d] ", topo->gt_id,
get_topo_name(topo->type), topo->type, topo->num_bytes, sz);
+
for (int j=0; j< topo->num_bytes; j++)
igt_info(" %02x", topo->mask[j]);
+
+ topo_types = 1 << topo->type;
igt_info("\n");
query.size -= sz;
pos += sz;
}
+ /* sanity check EU type */
+ if (IS_PONTEVECCHIO(dev_id) || AT_LEAST_GEN(dev_id, 20)) {
+ igt_assert(topo_types & (1 << LOCAL_DRM_XE_TOPO_SIMD16_EU_PER_DSS));
+ igt_assert_eq(topo_types & (1 << DRM_XE_TOPO_EU_PER_DSS), 0);
+ } else {
+ igt_assert(topo_types & (1 << DRM_XE_TOPO_EU_PER_DSS));
+ igt_assert_eq(topo_types & (1 << LOCAL_DRM_XE_TOPO_SIMD16_EU_PER_DSS), 0);
+ }
+
free(topology);
}
--
2.43.0
next reply other threads:[~2024-07-10 22:00 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 21:59 Lucas De Marchi [this message]
2024-07-10 22:25 ` [PATCH i-g-t v2] tests/intel/xe_query: Sanity check EU width Cavitt, Jonathan
2024-07-10 22:38 ` ✗ CI.xeBAT: failure for tests/intel/xe_query: Sanity check EU width (rev2) Patchwork
2024-07-10 22:39 ` ✓ Fi.CI.BAT: success " Patchwork
2024-07-11 0:19 ` ✗ CI.xeFULL: failure " Patchwork
2024-07-11 11:36 ` ✗ Fi.CI.IGT: " Patchwork
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