[PATCH v3 i-g-t 2/2] benchmarks/gem_wsim: Fix mmap for discrete graphics cards

[Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>]

It appears that 'gem_mmap__wc' doesn't work for discrete graphics cards
and 'I915_MMAP_OFFSET_FIXED' is needed instead.
Adopt the mapping approach from 'lib/igt_dummyload'.

v2: Correct brace balance (Kamil)
    Remove redundant 'ptr' variable

Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 benchmarks/gem_wsim.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index cd1a01a67..af30a22b3 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -1494,7 +1494,7 @@ static unsigned int create_bb(struct w_step *w, int self)
 #define TIMESTAMP (base + 0x3a8)
 	const int use_64b = gen >= 8;
 	enum { START_TS, NOW_TS };
-	uint32_t *ptr, *cs, *jmp;
+	uint32_t *cs, *jmp;
 	unsigned int r = 0;
 
 	/* Loop until CTX_TIMESTAMP - initial > target ns */
@@ -1502,7 +1502,16 @@ static unsigned int create_bb(struct w_step *w, int self)
 	gem_set_domain(fd, w->bb_handle,
 		       I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
 
-	cs = ptr = gem_mmap__wc(fd, w->bb_handle, 0, w->bb_size, PROT_WRITE);
+	if (__gem_set_caching(fd, w->bb_handle, I915_CACHING_CACHED) == 0) {
+		cs = gem_mmap__cpu(fd, w->bb_handle,
+				   0, w->bb_size,
+				   PROT_READ | PROT_WRITE);
+	} else {
+		cs = gem_mmap__device_coherent(fd,
+					       w->bb_handle,
+					       0, w->bb_size,
+					       PROT_READ | PROT_WRITE);
+	}
 
 	/* Store initial 64b timestamp: start */
 	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_CS_MMIO_DST;
-- 
2.31.1