Re: [PATCH v2] tests/intel/xe_exec_store: Modify test for Priority Mem Read feature

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Jul 30, 2024 at 03:54:34AM +0530, Pallavi Mishra wrote:
> Now that KMD supports Priority Mem Read feature, care needs to
> be taken to avoid RAW hazards which may get introduced due to
> unordered read and writes. Inorder to prevent this insert
> MI_MEM_FENCE which will ensure data coherency in such
> scenarios.
> 
> KMD patch to enable Priority Mem Read:
> https://patchwork.freedesktop.org/series/134038/
> 
> v2: Add graphics version check (Matt Roper)
> 
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> ---
>  include/intel_gpu_commands.h |  2 ++
>  tests/intel/xe_exec_store.c  | 20 ++++++++++++++------
>  2 files changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/include/intel_gpu_commands.h b/include/intel_gpu_commands.h
> index fe734c4bb..cd281ba89 100644
> --- a/include/intel_gpu_commands.h
> +++ b/include/intel_gpu_commands.h

I think the original intent was that this file would be directly copied
from the KMD header (similar to how we copy PCI ID headers and such),
but it looks like people have been adding new changes directly to the
IGT copy and causing it to diverge from the kernel.  So we can go ahead
and make the changes here for now, but someone will need to go back at
some point soon and do some extra work to get the kernel and IGT back in
sync again.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> @@ -89,6 +89,7 @@
>  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
>  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
>  #define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
> +#define   MI_MEM_FENCE		MI_INSTR(0x09, 0)
>  #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
>  #define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
>  #define   MI_SEMAPHORE_UPDATE	    (1<<21)
> @@ -192,6 +193,7 @@
>  #define MI_OPCODE(x)		(((x) >> 23) & 0x3f)
>  #define IS_MI_LRI_CMD(x)	(MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
>  #define MI_LRI_LEN(x)		(((x) & 0xff) + 1)
> +#define MI_WRITE_FENCE			(3 << 0)
>  
>  /*
>   * 3D instructions used by the kernel
> diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
> index c872c22d5..8e6ffee4a 100644
> --- a/tests/intel/xe_exec_store.c
> +++ b/tests/intel/xe_exec_store.c
> @@ -51,7 +51,8 @@ static void store_dword_batch(struct data *data, uint64_t addr, int value)
>  	data->addr = batch_addr;
>  }
>  
> -static void cond_batch(struct data *data, uint64_t addr, int value)
> +static void cond_batch(struct data *data, uint64_t addr, int value,
> +		       uint16_t dev_id)
>  {
>  	int b;
>  	uint64_t batch_offset = (char *)&(data->batch) - (char *)data;
> @@ -63,6 +64,10 @@ static void cond_batch(struct data *data, uint64_t addr, int value)
>  	data->batch[b++] = MI_ATOMIC | MI_ATOMIC_INC;
>  	data->batch[b++] = sdi_addr;
>  	data->batch[b++] = sdi_addr >> 32;
> +
> +	if (intel_graphics_ver(dev_id) >= IP_VER(20, 0))
> +		data->batch[b++] = MI_MEM_FENCE | MI_WRITE_FENCE;
> +
>  	data->batch[b++] = MI_CONDITIONAL_BATCH_BUFFER_END | MI_DO_COMPARE | 5 << 12 | 2;
>  	data->batch[b++] = value;
>  	data->batch[b++] = sdi_addr;
> @@ -101,7 +106,8 @@ static void persistance_batch(struct data *data, uint64_t addr)
>   * SUBTEST: basic-all
>   * Description: Test to verify store dword on all available engines.
>   */
> -static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instance *eci)
> +static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instance *eci,
> +		       uint16_t dev_id)
>  {
>  	struct drm_xe_sync sync[2] = {
>  		{ .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
> @@ -144,7 +150,7 @@ static void basic_inst(int fd, int inst_type, struct drm_xe_engine_class_instanc
>  	else if (inst_type == COND_BATCH) {
>  		/* A random value where it stops at the below value. */
>  		value = 20 + random() % 10;
> -		cond_batch(data, addr, value);
> +		cond_batch(data, addr, value, dev_id);
>  	}
>  	else
>  		igt_assert_f(inst_type < 2, "Entered wrong inst_type.\n");
> @@ -333,21 +339,23 @@ igt_main
>  {
>  	struct drm_xe_engine_class_instance *hwe;
>  	int fd;
> +	uint16_t dev_id;
>  	struct drm_xe_engine *engine;
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
>  		xe_device_get(fd);
> +		dev_id = intel_get_drm_devid(fd);
>  	}
>  
>  	igt_subtest("basic-store") {
>  		engine = xe_engine(fd, 1);
> -		basic_inst(fd, STORE, &engine->instance);
> +		basic_inst(fd, STORE, &engine->instance, dev_id);
>  	}
>  
>  	igt_subtest("basic-cond-batch") {
>  		engine = xe_engine(fd, 1);
> -		basic_inst(fd, COND_BATCH, &engine->instance);
> +		basic_inst(fd, COND_BATCH, &engine->instance, dev_id);
>  	}
>  
>  	igt_subtest_with_dynamic("basic-all") {
> @@ -356,7 +364,7 @@ igt_main
>  				      xe_engine_class_string(hwe->engine_class),
>  				      hwe->engine_instance,
>  				      hwe->gt_id);
> -			basic_inst(fd, STORE, hwe);
> +			basic_inst(fd, STORE, hwe, dev_id);
>  		}
>  	}
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation