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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2024 10:59:37.6803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a054476-14cc-46ab-1bf7-08dcb2190938 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6447 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" In the bad length case, when the header length has more than 4dwords than packet stream length then CPFW will pending on the stream data and raise a CP halt error which requires do the pipe reset. As to the orignal case of header length is smaller than PM4 stream length then the PM4 stream data may will create a bad opcode error which only requires the queue reset. So for testing the pipe reset need to update the header length bigger than the PM4 stream data length. Signed-off-by: Prike Liang --- lib/amdgpu/amd_ip_blocks.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c index f675b97dd..3ffacc065 100644 --- a/lib/amdgpu/amd_ip_blocks.c +++ b/lib/amdgpu/amd_ip_blocks.c @@ -189,7 +189,7 @@ gfx_ring_bad_write_linear(const struct amdgpu_ip_funcs *func, const struct amdgpu_ring_context *ring_context, uint32_t *pm4_dw, unsigned int cmd_error) { - uint32_t i, j; + uint32_t i, j, stream_length; i = 0; j = 0; @@ -198,6 +198,11 @@ gfx_ring_bad_write_linear(const struct amdgpu_ip_funcs *func, * But the range applies to all asics. * 0xcb-0xcf, 0xd2-0xef, 0xf1-0xfb */ + if (cmd_error == CMD_STREAM_EXEC_INVALID_PACKET_LENGTH) + stream_length = ring_context->write_length / 16; + else + stream_length = ring_context->write_length; + if (cmd_error == CMD_STREAM_EXEC_INVALID_OPCODE) ring_context->pm4[i++] = PACKET3(0xf2, 2 + ring_context->write_length); else if (cmd_error == CMD_STREAM_EXEC_INVALID_PACKET_LENGTH) @@ -223,7 +228,7 @@ gfx_ring_bad_write_linear(const struct amdgpu_ip_funcs *func, ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc); } - while (j++ < ring_context->write_length) + while (j++ < stream_length) ring_context->pm4[i++] = func->deadbeaf; *pm4_dw = i; return i; -- 2.34.1