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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 02:02:59.9610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 755922bd-a54d-42e9-9cc7-08dcbcce639e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8738 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Some APUs have address tweak secure mechanisms that encrypt destination data preventing it from matching the original data. Rework the test case to ensure compatibility with these APUs. Signed-off-by: Tim Huang --- tests/amdgpu/amd_security.c | 28 ++++++---------------------- 1 file changed, 6 insertions(+), 22 deletions(-) diff --git a/tests/amdgpu/amd_security.c b/tests/amdgpu/amd_security.c index ec6883d3d..024cadc05 100644 --- a/tests/amdgpu/amd_security.c +++ b/tests/amdgpu/amd_security.c @@ -147,8 +147,6 @@ amdgpu_bo_move(amdgpu_device_handle device, int fd, */ static const uint8_t secure_pattern[] = { 0x5A, 0xFE, 0x05, 0xEC }; -static const uint8_t secure_pattern2[] = { 0xDE, 0xAD, 0xBE, 0xEF }; - static void amdgpu_secure_bounce(amdgpu_device_handle device_handle, int fd, struct drm_amdgpu_info_hw_ip *sdma_info, @@ -209,27 +207,13 @@ amdgpu_secure_bounce(amdgpu_device_handle device_handle, int fd, amdgpu_bo_lcopy(device_handle, ring_context, ip_block, SECURE_BUFFER_SIZE, secure == true ? 1 : 0); - /* Verify the contents of Bob. */ - for (pp = (__typeof__(pp))ring_context->bo2_cpu; - pp < (__typeof__(pp)) ring_context->bo2_cpu + SECURE_BUFFER_SIZE; - pp += sizeof(secure_pattern)) { - r = memcmp(pp, secure_pattern, sizeof(secure_pattern)); - if (r) { - // test failure - igt_assert(false); - break; - } - } - /* Fill Bob with a pattern2 */ - for (pp = (__typeof__(pp))ring_context->bo2_cpu; - pp < (__typeof__(pp)) ring_context->bo2_cpu + SECURE_BUFFER_SIZE; - pp += sizeof(secure_pattern2)) - memcpy(pp, secure_pattern2, sizeof(secure_pattern2)); - /* Move Bob to the GTT domain. */ amdgpu_bo_move(device_handle, fd, ring_context, ip_block, AMDGPU_GEM_DOMAIN_GTT, 0); + /* Clean Alice first before do the copy from bob. */ + memset((void *)ring_context->bo_cpu, 0, SECURE_BUFFER_SIZE); + /* sDMA TMZ copy from Bob to Alice. * bo is a source ,bo2 is destination */ @@ -250,11 +234,11 @@ amdgpu_secure_bounce(amdgpu_device_handle device_handle, int fd, amdgpu_bo_lcopy(device_handle, ring_context, ip_block, SECURE_BUFFER_SIZE, secure == true ? 1 : 0); - /* Verify the content of Alice if it matches to pattern2*/ + /* Verify the content of Alice if it matches to pattern */ for (pp = (__typeof__(pp))ring_context->bo_cpu; pp < (__typeof__(pp)) ring_context->bo_cpu + SECURE_BUFFER_SIZE; - pp += sizeof(secure_pattern2)) { - r = memcmp(pp, secure_pattern2, sizeof(secure_pattern2)); + pp += sizeof(secure_pattern)) { + r = memcmp(pp, secure_pattern, sizeof(secure_pattern)); if (r) { // test failure igt_assert(false); -- 2.43.0