From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B91DCC5473A for ; Tue, 27 Aug 2024 16:54:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAAF110E3B4; Tue, 27 Aug 2024 16:54:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="foxRKVVc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id F3F2410E3B0 for ; Tue, 27 Aug 2024 16:54:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724777697; x=1756313697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DT0s2Qsw9jn34Gdo5WuVJrpTmljdv3XC1qMiZjcfRPU=; b=foxRKVVcwjHaq5CoqexUvXgs+7od8WRKwZI2vXR1dMi6uLreKWEUnUe9 4bHRDzz3T+Mkmd9vfpp2a2Jg7P068lkIwaSICH7M0vcjKfUGsXq+hnoy6 +d6XVO1CoEO+Szs88H4os8TrsDpvPg3V0dZFv9zc4sNy9r6Q4xaVqydaL VGPQbE5D8hCwM1R6kZ02M8xEKGkUpYtMVp1fw6cVSNfYheZKHKysNPbsK 1OJrsFTOmjS3p6aW0XTaMG3vAcCaaDaJUcMAdrI4DpTxAFHYc0xlwwjTK vycJ0EQ9i4GyF3h9Pcvv/KRx2/Fs+cInAmoYQs2VKWFq2jjzoff2zRvHm Q==; X-CSE-ConnectionGUID: AQjKVZAPTYaqEExJ8l4WLA== X-CSE-MsgGUID: p42Fh0kESAS36muLOIyD+A== X-IronPort-AV: E=McAfee;i="6700,10204,11177"; a="45787337" X-IronPort-AV: E=Sophos;i="6.10,180,1719903600"; d="scan'208";a="45787337" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 09:54:56 -0700 X-CSE-ConnectionGUID: qnqWOSuoRkO8t+h5TL+08A== X-CSE-MsgGUID: YincbPgvTCueqwujUi8drA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,180,1719903600"; d="scan'208";a="63640435" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 09:54:57 -0700 From: Lucas De Marchi To: igt-dev@lists.freedesktop.org Cc: Umesh Nerlige Ramappa , Lucas De Marchi Subject: [PATCH i-g-t v3 09/10] tests/intel/xe_drm_fdinfo: Use enum with expected load Date: Tue, 27 Aug 2024 09:54:48 -0700 Message-ID: <20240827165449.1706784-10-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240827165449.1706784-1-lucas.demarchi@intel.com> References: <20240827165449.1706784-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Do not let the execution flag dictate the result check, but rather be explicit what's being checked: idle or full load. Signed-off-by: Lucas De Marchi --- tests/intel/xe_drm_fdinfo.c | 45 +++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c index 23edeea40..d45e45c6b 100644 --- a/tests/intel/xe_drm_fdinfo.c +++ b/tests/intel/xe_drm_fdinfo.c @@ -68,6 +68,11 @@ IGT_TEST_DESCRIPTION("Read and verify drm client memory consumption and engine u #define TEST_TRAILING_IDLE (1 << 1) #define TEST_ISOLATION (1 << 2) +enum expected_load { + EXPECTED_LOAD_IDLE, + EXPECTED_LOAD_FULL, +}; + struct pceu_cycles { uint64_t cycles; uint64_t total_cycles; @@ -471,7 +476,7 @@ spin_ctx_destroy(int fd, struct spin_ctx *ctx) static void check_results(struct pceu_cycles *s1, struct pceu_cycles *s2, - int class, unsigned int flags) + int class, enum expected_load expected_load) { double percent; u64 den, num; @@ -487,11 +492,18 @@ check_results(struct pceu_cycles *s1, struct pceu_cycles *s2, igt_debug("%s: percent: %f\n", engine_map[class], percent); - if (flags & TEST_BUSY) { + switch (expected_load) { + case EXPECTED_LOAD_IDLE: + igt_assert_eq(num, 0); + break; + case EXPECTED_LOAD_FULL: + /* + * We are still relying on CPU sleep time and there could be + * some imprecision when calculating the load. Use a 5% margin. + */ igt_assert_lt_double(95.0, percent); igt_assert_lt_double(percent, 105.0); - } else { - igt_assert_eq(num, 0); + break; } } @@ -501,6 +513,7 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags) struct pceu_cycles pceu1[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1]; struct pceu_cycles pceu2[2][DRM_XE_ENGINE_CLASS_COMPUTE + 1]; struct spin_ctx *ctx = NULL; + enum expected_load expected_load; uint32_t vm; int new_fd; @@ -525,10 +538,16 @@ single(int fd, struct drm_xe_engine_class_instance *hwe, unsigned int flags) if (flags & TEST_ISOLATION) read_engine_cycles(new_fd, pceu2[1]); - check_results(pceu1[0], pceu2[0], hwe->engine_class, flags); + expected_load = flags & TEST_BUSY ? + EXPECTED_LOAD_FULL : EXPECTED_LOAD_IDLE; + check_results(pceu1[0], pceu2[0], hwe->engine_class, expected_load); if (flags & TEST_ISOLATION) { - check_results(pceu1[1], pceu2[1], hwe->engine_class, 0); + /* + * Load from one client shouldn't spill on another, + * so check for idle + */ + check_results(pceu1[1], pceu2[1], hwe->engine_class, EXPECTED_LOAD_IDLE); close(new_fd); } @@ -557,9 +576,10 @@ busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe) read_engine_cycles(fd, pceu2); xe_for_each_engine_class(class) { - bool idle = hwe->engine_class != class; + enum expected_load expected_load = hwe->engine_class != class ? + EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL; - check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY); + check_results(pceu1, pceu2, class, expected_load); } spin_sync_end(fd, ctx); @@ -590,7 +610,7 @@ single_destroy_queue(int fd, struct drm_xe_engine_class_instance *hwe) xe_vm_destroy(fd, vm); - check_results(pceu1, pceu2, hwe->engine_class, TEST_BUSY); + check_results(pceu1, pceu2, hwe->engine_class, EXPECTED_LOAD_FULL); } static void @@ -623,12 +643,13 @@ most_busy_check_all(int fd, struct drm_xe_engine_class_instance *hwe) read_engine_cycles(fd, pceu2); xe_for_each_engine_class(class) { - bool idle = hwe->engine_class == class; + enum expected_load expected_load = hwe->engine_class == class ? + EXPECTED_LOAD_IDLE : EXPECTED_LOAD_FULL; if (!ctx[class]) continue; - check_results(pceu1, pceu2, class, idle ? 0 : TEST_BUSY); + check_results(pceu1, pceu2, class, expected_load); spin_sync_end(fd, ctx[class]); spin_ctx_destroy(fd, ctx[class]); } @@ -668,7 +689,7 @@ all_busy_check_all(int fd) if (!ctx[class]) continue; - check_results(pceu1, pceu2, class, TEST_BUSY); + check_results(pceu1, pceu2, class, EXPECTED_LOAD_FULL); spin_sync_end(fd, ctx[class]); spin_ctx_destroy(fd, ctx[class]); } -- 2.43.0