[PATCH 1/2 V2 i-g-t] lib/amdgpu: Enhanced SDMA negative test interface

["Jesse.zhang@amd.com" <jesse.zhang@amd.com>]

To enhance the reset function, several invalid sdma writes are added.
1. Assembling invalid operation code.
2. Writing invalid memory address.
3. Writing illegal register.
4. Sending invalid packet length.

Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
---
 lib/amdgpu/amd_deadlock_helpers.h |  5 ---
 lib/amdgpu/amd_ip_blocks.c        | 51 +++++++++++++++++++++++++++++++
 lib/amdgpu/amd_ip_blocks.h        |  5 ++-
 3 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/lib/amdgpu/amd_deadlock_helpers.h b/lib/amdgpu/amd_deadlock_helpers.h
index e36227950..165ffb98d 100644
--- a/lib/amdgpu/amd_deadlock_helpers.h
+++ b/lib/amdgpu/amd_deadlock_helpers.h
@@ -24,11 +24,6 @@
 #ifndef __AMD_DEADLOCK_HELPERS_H__
 #define __AMD_DEADLOCK_HELPERS_H__
 
-enum  hang_type {
-	DMA_CORRUPTED_HEADER_HANG,
-	DMA_SLOW_LINEARCOPY_HANG
-};
-
 void
 amdgpu_wait_memory_helper(amdgpu_device_handle device_handle, unsigned int ip_type);
 
diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index 175c84cf9..a486347ac 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c
@@ -57,6 +57,56 @@ sdma_ring_write_linear(const struct amdgpu_ip_funcs *func,
 	return 0;
 }
 
+static int
+sdma_ring_bad_write_linear(const struct amdgpu_ip_funcs *func,
+		       const struct amdgpu_ring_context *ring_context,
+		       uint32_t *pm4_dw, unsigned int cmd_error)
+{
+	uint32_t i, j, stream_length;
+	uint32_t opcode;
+
+	i = 0;
+	j = 0;
+
+	if (cmd_error == CMD_STREAM_EXEC_INVALID_PACKET_LENGTH)
+		stream_length = ring_context->write_length / 16;
+	else
+		stream_length = ring_context->write_length;
+
+	if (cmd_error == CMD_STREAM_EXEC_INVALID_OPCODE)
+		opcode = 0xf2;
+	else
+		opcode = SDMA_OPCODE_WRITE;
+
+	if (func->family_id == AMDGPU_FAMILY_SI)
+		ring_context->pm4[i++] = SDMA_PACKET_SI(opcode, 0, 0, 0,
+					 ring_context->write_length);
+	else
+		ring_context->pm4[i++] = SDMA_PACKET(opcode,
+					 SDMA_WRITE_SUB_OPCODE_LINEAR,
+					 ring_context->secure ? SDMA_ATOMIC_TMZ(1) : 0);
+	if (cmd_error == CMD_STREAM_TRANS_BAD_MEM_ADDRESS) {
+		ring_context->pm4[i++] = lower_32_bits(0xdeadbee0);
+		ring_context->pm4[i++] = upper_32_bits(0xdeadbee0);
+	}else if (cmd_error == CMD_STREAM_TRANS_BAD_REG_ADDRESS) {
+		ring_context->pm4[i++] = lower_32_bits(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR);
+		ring_context->pm4[i++] = upper_32_bits(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR);
+	} else {
+		ring_context->pm4[i++] = lower_32_bits(ring_context->bo_mc);
+		ring_context->pm4[i++] = upper_32_bits(ring_context->bo_mc);
+	}
+	if (func->family_id >= AMDGPU_FAMILY_AI)
+		ring_context->pm4[i++] = ring_context->write_length - 1;
+	else
+		ring_context->pm4[i++] = ring_context->write_length;
+
+	while (j++ < stream_length)
+		ring_context->pm4[i++] = func->deadbeaf;
+	*pm4_dw = i;
+
+	return 0;
+}
+
 static int
 sdma_ring_atomic(const struct amdgpu_ip_funcs *func,
 		       const struct amdgpu_ring_context *ring_context,
@@ -429,6 +479,7 @@ static struct amdgpu_ip_funcs sdma_v3_x_ip_funcs = {
 	.deadbeaf = 0xdeadbeaf,
 	.pattern = 0xaaaaaaaa,
 	.write_linear = sdma_ring_write_linear,
+	.bad_write_linear = sdma_ring_bad_write_linear,
 	.write_linear_atomic = sdma_ring_atomic,
 	.const_fill = sdma_ring_const_fill,
 	.copy_linear = sdma_ring_copy_linear,
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 86b82c40c..3e729f4c0 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -42,7 +42,10 @@ enum  cmd_error_type {
 	BACKEND_SE_GC_SHADER_INVALID_SHADER,
 	BACKEND_SE_GC_SHADER_INVALID_PROGRAM_ADDR,    /* COMPUTE_PGM */
 	BACKEND_SE_GC_SHADER_INVALID_PROGRAM_SETTING, /* COMPUTE_PGM_RSRC */
-	BACKEND_SE_GC_SHADER_INVALID_USER_DATA /* COMPUTE_USER_DATA */
+	BACKEND_SE_GC_SHADER_INVALID_USER_DATA, /* COMPUTE_USER_DATA */
+
+	DMA_CORRUPTED_HEADER_HANG,
+	DMA_SLOW_LINEARCOPY_HANG
 };
 
 #define _MAX_NUM_ASIC_ID_EXCLUDE_FILTER 3
-- 
2.25.1