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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2024 03:36:46.3370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0275c955-6b46-4dbb-1c36-08dccb0078aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5675 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To enhance queue reset, add sdma ip test. v3: 1.add sdma support flag, 2.add a function about calcuating num of tests, 3.Remove !strstr(it->name, "CMD").(Vitaly) Cc: Vitaly Prosyak Cc: Alex Deucher Cc: Christian Koenig Signed-off-by: Jesse Zhang Reviewed-by: Vitaly Prosyak --- lib/amdgpu/amd_ip_blocks.h | 1 + tests/amdgpu/amd_queue_reset.c | 43 +++++++++++++++++++++++++--------- 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h index 3e729f4c0..6a8f97d24 100644 --- a/lib/amdgpu/amd_ip_blocks.h +++ b/lib/amdgpu/amd_ip_blocks.h @@ -62,6 +62,7 @@ struct dynamic_test{ const char *name; const char *describe; struct asic_id_filter exclude_filter[_MAX_NUM_ASIC_ID_EXCLUDE_FILTER]; + bool support_sdma; }; #define for_each_test(t, T) for(typeof(*T) *t = T; t->name; t++) diff --git a/tests/amdgpu/amd_queue_reset.c b/tests/amdgpu/amd_queue_reset.c index 537f653f9..b257ec3c0 100644 --- a/tests/amdgpu/amd_queue_reset.c +++ b/tests/amdgpu/amd_queue_reset.c @@ -1022,6 +1022,23 @@ reset_rings_numbers(unsigned int *ring_id_good, unsigned int *ring_id_bad, *ring_id_job_bad = 0; } +static int +get_num_of_tests(struct dynamic_test *arr_err, enum amd_ip_block_type *ip_tests, int num_ip) +{ + int i, cnt=0; + + for (i = 0; i < num_ip; i++) { + for (struct dynamic_test *it = arr_err; it->name; it++) { + if(*ip_tests == AMD_IP_DMA && (!it->support_sdma)) + continue; + cnt++; + } + ip_tests++; + } + + return cnt; +} + igt_main { char cmdline[2048]; @@ -1035,7 +1052,6 @@ igt_main posix_spawn_file_actions_t action; amdgpu_device_handle device; struct amdgpu_gpu_info gpu_info = {0}; - struct drm_amdgpu_info_hw_ip info[2] = {0}; int fd = -1; int fd_shm = -1; struct shmbuf *sh_mem = NULL; @@ -1047,8 +1063,9 @@ igt_main unsigned int ring_id_job_good; unsigned int ring_id_job_bad; - enum amd_ip_block_type ip_tests[2] = {AMD_IP_COMPUTE/*keep first*/, AMD_IP_GFX}; + enum amd_ip_block_type ip_tests[] = {AMD_IP_COMPUTE/*keep first*/, AMD_IP_GFX, AMD_IP_DMA}; enum amd_ip_block_type ip_background = AMD_IP_COMPUTE; + struct drm_amdgpu_info_hw_ip info[ARRAY_SIZE(ip_tests)] = {0}; amdgpu_context_handle *arr_context_handle = NULL; @@ -1059,10 +1076,10 @@ igt_main struct dynamic_test arr_err[] = { {CMD_STREAM_EXEC_INVALID_PACKET_LENGTH, "CMD_STREAM_EXEC_INVALID_PACKET_LENGTH", "Stressful-and-multiple-cs-of-bad and good length-operations-using-multiple-processes", - { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } } }, + { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } }, true }, {CMD_STREAM_EXEC_INVALID_OPCODE, "CMD_STREAM_EXEC_INVALID_OPCODE", "Stressful-and-multiple-cs-of-bad and good opcode-operations-using-multiple-processes", - { {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_UNKNOWN, -1, -1 } } }, + { {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_UNKNOWN, -1, -1 } }, true }, //TODO not job timeout, debug why for n31. //{CMD_STREAM_TRANS_BAD_MEM_ADDRESS_BY_SYNC,"CMD_STREAM_TRANS_BAD_MEM_ADDRESS_BY_SYNC", // "Stressful-and-multiple-cs-of-bad and good mem-sync-operations-using-multiple-processes"}, @@ -1071,16 +1088,16 @@ igt_main // "Stressful-and-multiple-cs-of-bad and good reg-operations-using-multiple-processes"}, {BACKEND_SE_GC_SHADER_INVALID_PROGRAM_ADDR, "BACKEND_SE_GC_SHADER_INVALID_PROGRAM_ADDR", "Stressful-and-multiple-cs-of-bad and good shader-operations-using-multiple-processes", - { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } } }, + { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } }, false }, //TODO KGQ cannot recover by queue reset, it maybe need a fw bugfix on naiv31 //{BACKEND_SE_GC_SHADER_INVALID_PROGRAM_SETTING,"BACKEND_SE_GC_SHADER_INVALID_PROGRAM_SETTING", // "Stressful-and-multiple-cs-of-bad and good shader-operations-using-multiple-processes"}, {BACKEND_SE_GC_SHADER_INVALID_USER_DATA, "BACKEND_SE_GC_SHADER_INVALID_USER_DATA", "Stressful-and-multiple-cs-of-bad and good shader-operations-using-multiple-processes", - { {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } } }, + { {FAMILY_UNKNOWN, -1, -1 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } }, false }, {BACKEND_SE_GC_SHADER_INVALID_SHADER, "BACKEND_SE_GC_SHADER_INVALID_SHADER", "Stressful-and-multiple-cs-of-bad and good shader-operations-using-multiple-processes", - { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } } }, + { {FAMILY_UNKNOWN, 0x1, 0x10 }, {FAMILY_AI, 0x32, 0x3C }, {FAMILY_AI, 0x3C, 0xFF } }, false }, {} }; @@ -1098,8 +1115,7 @@ igt_main if (is_run_subtest_parameter_found(argc, argv)) const_num_of_tests = 1; else - const_num_of_tests = (sizeof(arr_err)/sizeof(struct dynamic_test) - 1) * ARRAY_SIZE(ip_tests); - + const_num_of_tests = get_num_of_tests(&arr_err[0], &ip_tests[0], ARRAY_SIZE(ip_tests)); fd = drm_open_driver(DRIVER_AMDGPU); err = amdgpu_device_initialize(fd, &major, &minor, &device); @@ -1139,16 +1155,21 @@ igt_main process, sh_mem, const_num_of_tests, info[0].hw_ip_version_major, &monitor_child, &test_child); } + for (int i = 0; i < ARRAY_SIZE(ip_tests); i++) { reset_rings_numbers(&ring_id_good, &ring_id_bad, &ring_id_job_good, &ring_id_job_bad); for (struct dynamic_test *it = &arr_err[0]; it->name; it++) { + if(ip_tests[i] == AMD_IP_DMA && (!it->support_sdma)) + continue; igt_describe("Stressful-and-multiple-cs-of-bad-and-good-length-operations-using-multiple-processes"); - igt_subtest_with_dynamic_f("amdgpu-%s-%s", ip_tests[i] == AMD_IP_COMPUTE ? "COMPUTE":"GFX", it->name) { + igt_subtest_with_dynamic_f("amdgpu-%s-%s", ip_tests[i] == AMD_IP_COMPUTE ? "COMPUTE": + ip_tests[i] == AMD_IP_GFX ? "GFX":"SDMA", it->name) { if (arr_cap[ip_tests[i]] && is_sub_test_queue_reset_enable(&gpu_info, it->exclude_filter, it) && get_next_rings(&ring_id_good, &ring_id_bad, info[0].available_rings, info[i].available_rings, ip_background != ip_tests[i], &ring_id_job_good, &ring_id_job_bad)) { igt_dynamic_f("amdgpu-%s-ring-good-%d-bad-%d-%s", it->name, ring_id_job_good, ring_id_job_bad, - ip_tests[i] == AMD_IP_COMPUTE ? "COMPUTE":"GFX") + ip_tests[i] == AMD_IP_COMPUTE ? "COMPUTE": + ip_tests[i] == AMD_IP_GFX? "GFX":"SDMA") set_next_test_to_run(sh_mem, it->test, ip_background, ip_tests[i], ring_id_job_good, ring_id_job_bad); } else { set_next_test_to_skip(sh_mem); -- 2.25.1