From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 452E7CD4F5F for ; Thu, 5 Sep 2024 09:28:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01EAF10E804; Thu, 5 Sep 2024 09:28:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JlKqwPsP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87F2B10E805 for ; Thu, 5 Sep 2024 09:28:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725528527; x=1757064527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2NR2iWcFxF9fkEV+ca/YYU4BG9u0G+Ec7UpJRwBLCHg=; b=JlKqwPsPiSoAq6ICV9c/VqFwPPQiUThSA1CU2lJKLFxgiydZeanNdVp+ DGKJdRN2m7H2RRsR3Cg5EuDZBUQpfXDSoE4kokZHAuAfCiiBdQtas8YFl ZQudt5Kz7+zLkZtbIEHg37iiHuf75ysiUo98ZU9gsHs0+v6ydeskG9KaS K3k4Tm6XTaFo1BOLKkQ9RgSFvB+GRG7/2tUbdkr0lutfEiE6tDELc2EOy Ge3lPoxC9Aug3IJwXZub/eVqTZ/qU9knfllvIoXHm/p6cEv7ZVIEMTsLh U0icm1qH5iZ6O99vyHxMMfk4oMM8NiZyyGTrEbVLT3TFKGl7+8+WbmG7l w==; X-CSE-ConnectionGUID: rsvoQhHmQd+pvOQINrSvIw== X-CSE-MsgGUID: pChFOrK1TK+du/dwHxrlxA== X-IronPort-AV: E=McAfee;i="6700,10204,11185"; a="35590182" X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="35590182" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 02:28:46 -0700 X-CSE-ConnectionGUID: LyzMYIdUQfGP0qsl4pFrmA== X-CSE-MsgGUID: noWJ8cqdS4uYwAaI5a54iw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="65404763" Received: from kniemiec-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.246.144]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 02:28:41 -0700 From: Christoph Manszewski To: igt-dev@lists.freedesktop.org Cc: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= , Kamil Konieczny , Dominik Grzegorzek , Maciej Patelczyk , =?UTF-8?q?Dominik=20Karol=20Pi=C4=85tkowski?= , Pawel Sikora , Andrzej Hajda , Kolanupaka Naveena , Mika Kuoppala , Gwan-gyeong Mun , Christoph Manszewski Subject: [PATCH i-g-t v6 05/17] lib/gpgpu_shader: Add set/clear exception register (cr0.1) helpers Date: Thu, 5 Sep 2024 11:28:00 +0200 Message-Id: <20240905092812.94553-6-christoph.manszewski@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240905092812.94553-1-christoph.manszewski@intel.com> References: <20240905092812.94553-1-christoph.manszewski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" From: Andrzej Hajda To allow enabling and handling exceptions from shader and siplet proper helpers should be provided. Signed-off-by: Andrzej Hajda Signed-off-by: Christoph Manszewski Reviewed-by: Zbigniew Kempczyński --- lib/gpgpu_shader.c | 28 ++++++++++++++++++++++ lib/gpgpu_shader.h | 2 ++ lib/iga64_generated_codes.c | 48 ++++++++++++++++++++++++++++++++++++- 3 files changed, 77 insertions(+), 1 deletion(-) diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c index 926eccaa0..9284ad5ea 100644 --- a/lib/gpgpu_shader.c +++ b/lib/gpgpu_shader.c @@ -634,6 +634,34 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value, ", 2, y_offset, 3, value, value, value, value); } +/** + * gpgpu_shader__clear_exception: + * @shdr: shader to be modified + * @value: exception bits to be cleared + * + * Clear provided bits in exception register: cr0.1 &= ~value. + */ +void gpgpu_shader__clear_exception(struct gpgpu_shader *shdr, uint32_t value) +{ + emit_iga64_code(shdr, clear_exception, " \n\ +(W) and (1|M0) cr0.1<1>:ud cr0.1<0;1,0>:ud ARG(0):ud \n\ + ", ~value); +} + +/** + * gpgpu_shader__set_exception: + * @shdr: shader to be modified + * @value: exception bits to be set + * + * Set provided bits in exception register: cr0.1 |= value. + */ +void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value) +{ + emit_iga64_code(shdr, set_exception, " \n\ +(W) or (1|M0) cr0.1<1>:ud cr0.1<0;1,0>:ud ARG(0):ud \n\ + ", value); +} + /** * gpgpu_shader__write_on_exception: * @shdr: shader to be modified diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h index 6c6953a1a..b722b9e50 100644 --- a/lib/gpgpu_shader.h +++ b/lib/gpgpu_shader.h @@ -71,6 +71,8 @@ void gpgpu_shader__common_target_write(struct gpgpu_shader *shdr, uint32_t y_offset, const uint32_t value[4]); void gpgpu_shader__common_target_write_u32(struct gpgpu_shader *shdr, uint32_t y_offset, uint32_t value); +void gpgpu_shader__clear_exception(struct gpgpu_shader *shdr, uint32_t value); +void gpgpu_shader__set_exception(struct gpgpu_shader *shdr, uint32_t value); void gpgpu_shader__end_system_routine(struct gpgpu_shader *shdr, bool breakpoint_suppress); void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr, diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c index 0800496c5..e1c3adf80 100644 --- a/lib/iga64_generated_codes.c +++ b/lib/iga64_generated_codes.c @@ -3,7 +3,7 @@ #include "gpgpu_shader.h" -#define MD5_SUM_IGA64_ASMS 716c5b437e2abd2a1768e79182993ff6 +#define MD5_SUM_IGA64_ASMS 75f01a0931a6c846c506d943aab8f727 struct iga64_template const iga64_code_gpgpu_fill[] = { { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) { @@ -277,6 +277,52 @@ struct iga64_template const iga64_code_write_on_exception[] = { }} }; +struct iga64_template const iga64_code_set_exception[] = { + { .gen_ver = 2000, .size = 8, .code = (const uint32_t []) { + 0x80000966, 0x80118220, 0x02008010, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1270, .size = 8, .code = (const uint32_t []) { + 0x80000966, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1260, .size = 8, .code = (const uint32_t []) { + 0x80000966, 0x80118220, 0x02008010, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1250, .size = 8, .code = (const uint32_t []) { + 0x80000966, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 0, .size = 8, .code = (const uint32_t []) { + 0x80000166, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000101, 0x00010000, 0x00000000, 0x00000000, + }} +}; + +struct iga64_template const iga64_code_clear_exception[] = { + { .gen_ver = 2000, .size = 8, .code = (const uint32_t []) { + 0x80000965, 0x80118220, 0x02008010, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1270, .size = 8, .code = (const uint32_t []) { + 0x80000965, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1260, .size = 8, .code = (const uint32_t []) { + 0x80000965, 0x80118220, 0x02008010, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 1250, .size = 8, .code = (const uint32_t []) { + 0x80000965, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000901, 0x00010000, 0x00000000, 0x00000000, + }}, + { .gen_ver = 0, .size = 8, .code = (const uint32_t []) { + 0x80000165, 0x80218220, 0x02008020, 0xc0ded000, + 0x80000101, 0x00010000, 0x00000000, 0x00000000, + }} +}; + struct iga64_template const iga64_code_media_block_write[] = { { .gen_ver = 2000, .size = 56, .code = (const uint32_t []) { 0x80100061, 0x04054220, 0x00000000, 0x00000000, -- 2.34.1