From: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
To: igt-dev@lists.freedesktop.org
Cc: adam.miszczak@linux.intel.com, jakub1.kolakowski@intel.com,
lukasz.laguna@intel.com, michal.wajdeczko@intel.com,
michal.winiarski@intel.com, narasimha.c.v@intel.com,
piotr.piorkowski@intel.com, satyanarayana.k.v.p@intel.com,
tomasz.lis@intel.com,
Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Subject: [PATCH v2 i-g-t 6/6] tests/intel/xe_sriov_flr: Implement clear-scratch-regs and clear-media-scratch-regs subchecks
Date: Mon, 21 Oct 2024 22:07:37 +0200 [thread overview]
Message-ID: <20241021200737.941384-7-marcin.bernatowicz@linux.intel.com> (raw)
In-Reply-To: <20241021200737.941384-1-marcin.bernatowicz@linux.intel.com>
Add tests to verify clearing of scratch and media scratch registers in
Virtual Functions (VFs) after a Functional Level Reset (FLR).
This code is based on prior work of Lukasz Laguna.
v2: Adjust mmio to align VF index with array index (Lukasz)
Use helpers for setting skip/fail reasons to improve readability
Signed-off-by: Marcin Bernatowicz <marcin.bernatowicz@linux.intel.com>
Cc: Adam Miszczak <adam.miszczak@linux.intel.com>
Cc: Jakub Kolakowski <jakub1.kolakowski@intel.com>
Cc: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: Michał Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Narasimha C V <narasimha.c.v@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
---
tests/intel/xe_sriov_flr.c | 122 ++++++++++++++++++++++++++++++++++++-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/tests/intel/xe_sriov_flr.c b/tests/intel/xe_sriov_flr.c
index 1ee724fac..5fc1baf96 100644
--- a/tests/intel/xe_sriov_flr.c
+++ b/tests/intel/xe_sriov_flr.c
@@ -7,6 +7,7 @@
#include <sys/stat.h>
#include "drmtest.h"
#include "igt_core.h"
+#include "igt_device.h"
#include "igt_sriov_device.h"
#include "intel_chipset.h"
#include "linux_scaffold.h"
@@ -739,6 +740,95 @@ static void lmem_subcheck_cleanup(struct subcheck_data *data)
free(ldata->vf_lmem_size);
}
+#define SCRATCH_REG 0x190240
+#define SCRATCH_REG_COUNT 4
+#define MED_SCRATCH_REG 0x190310
+#define MED_SCRATCH_REG_COUNT 4
+
+struct regs_data {
+ struct subcheck_data base;
+ struct intel_mmio_data *mmio;
+ uint32_t reg_addr;
+ int reg_count;
+};
+
+static void regs_subcheck_init(struct subcheck_data *data)
+{
+ struct regs_data *rdata = (struct regs_data *)data;
+
+ if (!xe_has_media_gt(data->pf_fd) &&
+ rdata->reg_addr == MED_SCRATCH_REG) {
+ set_skip_reason(data, "No media GT\n");
+ }
+}
+
+static void regs_subcheck_prepare_vf(int vf_id, struct subcheck_data *data)
+{
+ struct regs_data *rdata = (struct regs_data *)data;
+ uint32_t reg;
+ int i;
+
+ if (data->stop_reason)
+ return;
+
+ if (!is_intel_mmio_initialized(&rdata->mmio[vf_id])) {
+ struct pci_device *pci_dev = __igt_device_get_pci_device(data->pf_fd, vf_id);
+
+ if (!pci_dev) {
+ set_fail_reason(data, "No PCI device found for VF%u\n", vf_id);
+ return;
+ }
+
+ if (intel_register_access_init(&rdata->mmio[vf_id], pci_dev, false)) {
+ set_fail_reason(data, "Failed to get access to VF%u MMIO\n", vf_id);
+ return;
+ }
+ }
+
+ for (i = 0; i < rdata->reg_count; i++) {
+ reg = rdata->reg_addr + i * 4;
+
+ intel_register_write(&rdata->mmio[vf_id], reg, vf_id);
+ if (intel_register_read(&rdata->mmio[vf_id], reg) != vf_id) {
+ set_fail_reason(data, "Registers write/read check failed on VF%u\n", vf_id);
+ return;
+ }
+ }
+}
+
+static void regs_subcheck_verify_vf(int vf_id, int flr_vf_id, struct subcheck_data *data)
+{
+ struct regs_data *rdata = (struct regs_data *)data;
+ uint32_t expected = (vf_id == flr_vf_id) ? 0 : vf_id;
+ uint32_t reg;
+ int i;
+
+ if (data->stop_reason)
+ return;
+
+ for (i = 0; i < rdata->reg_count; i++) {
+ reg = rdata->reg_addr + i * 4;
+
+ if (intel_register_read(&rdata->mmio[vf_id], reg) != expected) {
+ set_fail_reason(data,
+ "Registers check after VF%u FLR failed on VF%u\n",
+ flr_vf_id, vf_id);
+ return;
+ }
+ }
+}
+
+static void regs_subcheck_cleanup(struct subcheck_data *data)
+{
+ struct regs_data *rdata = (struct regs_data *)data;
+ int i;
+
+ if (rdata->mmio)
+ for (i = 1; i <= data->num_vfs; ++i)
+ if (is_intel_mmio_initialized(&rdata->mmio[i]))
+ intel_register_access_fini(&rdata->mmio[i]);
+}
+
static void clear_tests(int pf_fd, int num_vfs)
{
struct xe_mmio xemmio = { };
@@ -747,10 +837,25 @@ static void clear_tests(int pf_fd, int num_vfs)
struct lmem_data ldata = {
.base = { .pf_fd = pf_fd, .num_vfs = num_vfs }
};
- const unsigned int num_checks = num_gts + 1;
+ struct intel_mmio_data mmio[num_vfs + 1];
+ struct regs_data scratch_data = {
+ .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
+ .mmio = mmio,
+ .reg_addr = SCRATCH_REG,
+ .reg_count = SCRATCH_REG_COUNT
+ };
+ struct regs_data media_scratch_data = {
+ .base = { .pf_fd = pf_fd, .num_vfs = num_vfs },
+ .mmio = mmio,
+ .reg_addr = MED_SCRATCH_REG,
+ .reg_count = MED_SCRATCH_REG_COUNT
+ };
+ const unsigned int num_checks = num_gts + 3;
struct subcheck checks[num_checks];
int i;
+ memset(mmio, 0, sizeof(mmio));
+
for (i = 0; i < num_gts; ++i) {
gdata[i] = (struct ggtt_data){
.base = { .pf_fd = pf_fd, .num_vfs = num_vfs, .gt = i },
@@ -772,6 +877,21 @@ static void clear_tests(int pf_fd, int num_vfs)
.prepare_vf = lmem_subcheck_prepare_vf,
.verify_vf = lmem_subcheck_verify_vf,
.cleanup = lmem_subcheck_cleanup };
+ checks[i++] = (struct subcheck) {
+ .data = (struct subcheck_data *)&scratch_data,
+ .name = "clear-scratch-regs",
+ .init = regs_subcheck_init,
+ .prepare_vf = regs_subcheck_prepare_vf,
+ .verify_vf = regs_subcheck_verify_vf,
+ .cleanup = regs_subcheck_cleanup };
+ checks[i++] = (struct subcheck) {
+ .data = (struct subcheck_data *)&media_scratch_data,
+ .name = "clear-media-scratch-regs",
+ .init = regs_subcheck_init,
+ .prepare_vf = regs_subcheck_prepare_vf,
+ .verify_vf = regs_subcheck_verify_vf,
+ .cleanup = regs_subcheck_cleanup
+ };
igt_assert_eq(i, num_checks);
verify_flr(pf_fd, num_vfs, checks, num_checks);
--
2.31.1
next prev parent reply other threads:[~2024-10-21 20:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 20:07 [PATCH v2 i-g-t 0/6] Introduce xe_sriov_flr test Marcin Bernatowicz
2024-10-21 20:07 ` [PATCH v2 i-g-t 1/6] lib/igt_sriov_device: add helper for opening SR-IOV device sysfs Marcin Bernatowicz
2024-10-21 20:07 ` [PATCH v2 i-g-t 2/6] lib/igt_sriov_device: add helper for resetting SR-IOV device Marcin Bernatowicz
2024-10-22 10:10 ` Michal Wajdeczko
2024-10-23 14:23 ` Bernatowicz, Marcin
2024-10-21 20:07 ` [PATCH v2 i-g-t 3/6] tests/intel/xe_sriov_flr: Add skeleton for clear and isolation tests Marcin Bernatowicz
2024-10-21 20:07 ` [PATCH v2 i-g-t 4/6] tests/intel/xe_sriov_flr: Implement clear-ggtt subcheck Marcin Bernatowicz
2024-10-21 20:07 ` [PATCH v2 i-g-t 5/6] tests/intel/xe_sriov_flr: Implement clear-lmem subcheck Marcin Bernatowicz
2024-10-21 20:07 ` Marcin Bernatowicz [this message]
2024-10-21 21:41 ` ✓ Fi.CI.BAT: success for Introduce xe_sriov_flr test (rev2) Patchwork
2024-10-21 21:51 ` ✓ CI.xeBAT: " Patchwork
2024-10-22 3:56 ` ✗ CI.xeFULL: failure " Patchwork
2024-10-22 5:07 ` ✗ Fi.CI.IGT: " Patchwork
2024-10-28 14:29 ` [PATCH v2 i-g-t 0/6] Introduce xe_sriov_flr test Laguna, Lukasz
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