From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76E77D1266B for ; Tue, 5 Nov 2024 09:29:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3659410E545; Tue, 5 Nov 2024 09:29:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aFUMRbFQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 559E410E545 for ; Tue, 5 Nov 2024 09:29:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730798981; x=1762334981; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=au45zQzf/9aMxreByD56zfjz0dWXTyMlcXH4cN9Q/b4=; b=aFUMRbFQKB0KK89FEfhltMWCPMU0uXQHJEwUXNzpQOKSagEccoj+sSfB TdbYuB6RNCeQJLcRvAT+8+igTW4bZPw9EbYjgqtWTMlck1SAB/AhRRLFe j3fWEOpMZggMQN3RO/VCM1Xl9C+O4x+DeOhFIqG75uIjZoxV1NQ8/3OZC 7pC8qFt6EOx7W4c0p+RoigDRUhKwlXoNrw6L+y4yjr+NXqk2UbCLxoG3Q TiWPLWZczHW+M8FEbQH1C0Fl2GhlS/t0PGRTzSZinmt9DLYlZBrIhiZTG zJs4uQ1y9H0Cr/W4FdAsYWnlH8Diy41NI7Tc2JwZzT2bkjVrhzxiaazHg Q==; X-CSE-ConnectionGUID: v/46dpC8RxaDVdXyzGoEoQ== X-CSE-MsgGUID: PxVjRlEyQF+et5mY4G9MIg== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="33372462" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="33372462" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 01:29:41 -0800 X-CSE-ConnectionGUID: u1dvj3L9RxyZXlBUUmKbow== X-CSE-MsgGUID: tys5TxZ8SkGhB3swshdVkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="83831291" Received: from pgurram-desk.iind.intel.com ([10.145.169.87]) by orviesa009.jf.intel.com with ESMTP; 05 Nov 2024 01:29:40 -0800 From: Pravalika Gurram To: igt-dev@lists.freedesktop.org Cc: Pravalika Gurram , =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= Subject: [PATCH] tests/xe_spin_batch: Add spin-timestamp-check Date: Tue, 5 Nov 2024 14:58:05 +0530 Message-Id: <20241105092805.317286-1-pravalika.gurram@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" check the ctx_timestamp register post gt reset for each engine. Reference: VLK-64943 Signed-off-by: Pravalika Gurram Signed-off-by: Zbigniew Kempczyński --- tests/intel/xe_spin_batch.c | 158 ++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c index 9314e229e..547cb1c5b 100644 --- a/tests/intel/xe_spin_batch.c +++ b/tests/intel/xe_spin_batch.c @@ -309,6 +309,158 @@ static void xe_spin_fixed_duration(int fd, int gt, int class, int flags) put_ahnd(ahnd); } +static void exec_store(int fd, struct drm_xe_engine_class_instance *eci, + bool hang) +{ + uint64_t ahnd, bb_size, bb_addr; + uint32_t vm, exec_queue, bb; +#define USER_FENCE_VALUE 0xdeadbeefdeadbeefull + struct drm_xe_sync syncobj = { + .type = DRM_XE_SYNC_TYPE_USER_FENCE, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + .timeline_value = USER_FENCE_VALUE, + }; + + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&syncobj), + }; + struct { + uint32_t batch[16]; + uint64_t pad; + uint32_t data; + uint64_t vm_sync; + uint64_t exec_sync; + } *data; + uint64_t batch_offset, batch_addr, sdi_offset, sdi_addr; + int64_t timeout = NSEC_PER_SEC; + int i, ret; + + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); + + vm = xe_vm_create(fd, 0, 0); + exec_queue = xe_exec_queue_create(fd, vm, eci, 0); + bb_size = xe_bb_size(fd, sizeof(*data)); + bb = xe_bo_create(fd, vm, bb_size, vram_if_possible(fd, eci->gt_id), 0); + bb_addr = intel_allocator_alloc_with_strategy(ahnd, bb, bb_size, 0, + ALLOC_STRATEGY_LOW_TO_HIGH); + data = xe_bo_map(fd, bb, bb_size); + syncobj.addr = to_user_pointer(&data->vm_sync); + xe_vm_bind_async(fd, vm, 0, bb, 0, bb_addr, bb_size, &syncobj, 1); + xe_wait_ufence(fd, &data->vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + + batch_offset = (char *)&data->batch - (char *)data; + batch_addr = bb_addr + batch_offset; + sdi_offset = (char *)&data->data - (char *)data; + sdi_addr = bb_addr + sdi_offset; + + i = 0; + + data->batch[i++] = MI_STORE_DWORD_IMM_GEN4; + data->batch[i++] = sdi_addr; + data->batch[i++] = sdi_addr >> 32; + data->batch[i++] = 0; + if (!hang) + data->batch[i++] = MI_BATCH_BUFFER_END; + igt_assert(i <= ARRAY_SIZE(data->batch)); + + syncobj.addr = bb_addr + (char *)&data->exec_sync - (char *)data; + exec.exec_queue_id = exec_queue; + exec.address = batch_addr; + ret = __xe_exec(fd, &exec); + ret = __xe_wait_ufence(fd, &data->exec_sync, USER_FENCE_VALUE, 0, &timeout); + igt_assert(hang ? ret < 0 : ret == 0); + + munmap(data, bb_size); + gem_close(fd, bb); + + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); + + put_ahnd(ahnd); +} + +static void run_spinner(int fd, struct drm_xe_engine_class_instance *eci) +{ + struct drm_xe_sync sync = { + .type = DRM_XE_SYNC_TYPE_USER_FENCE, + .flags = DRM_XE_SYNC_FLAG_SIGNAL, + .timeline_value = USER_FENCE_VALUE, + }; + struct drm_xe_exec exec = { + .num_batch_buffer = 1, + .num_syncs = 1, + .syncs = to_user_pointer(&sync), + }; + struct xe_spin *spin; + uint64_t vm_sync; + size_t bo_size; + uint32_t vm; + uint32_t exec_queue; + uint64_t spin_addr; + uint64_t ahnd; + uint32_t bo; + uint32_t ts_1, ts_2; + + vm = xe_vm_create(fd, 0, 0); + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC); + bo_size = xe_bb_size(fd, sizeof(*spin)); + bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, eci->gt_id), 0); + spin = xe_bo_map(fd, bo, bo_size); + + exec_queue = xe_exec_queue_create(fd, vm, eci, 0); + spin_addr = intel_allocator_alloc_with_strategy(ahnd, bo, bo_size, 0, + ALLOC_STRATEGY_LOW_TO_HIGH); + + sync.addr = to_user_pointer(&vm_sync); + xe_vm_bind_async(fd, vm, 0, bo, 0, spin_addr, bo_size, &sync, 1); + xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + + + xe_spin_init_opts(spin, .addr = spin_addr, .write_timestamp = true); + sync.addr = spin_addr + (char *)&spin->exec_sync - (char *)spin; + exec.exec_queue_id = exec_queue; + exec.address = spin_addr; + xe_exec(fd, &exec); + xe_spin_wait_started(spin); + + /* Collect and check timestamps before stopping the spinner */ + usleep(50000); + ts_1 = spin->timestamp; + usleep(50000); + ts_2 = spin->timestamp; + igt_assert_neq_u32(ts_1, ts_2); + + xe_spin_end(spin); + xe_wait_ufence(fd, &spin->exec_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + + sync.addr = to_user_pointer(&vm_sync); + xe_vm_unbind_async(fd, vm, 0, 0, spin_addr, bo_size, &sync, 1); + xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC); + munmap(spin, bo_size); + gem_close(fd, bo); + + xe_exec_queue_destroy(fd, exec_queue); + xe_vm_destroy(fd, vm); + put_ahnd(ahnd); +} + +/** + * SUBTEST: spin-timestamp-check + * Description: Intiate gt reset then check the timestamp register for each engine. + * Test category: functionality test + */ +static void xe_spin_timestamp_check(int fd, struct drm_xe_engine_class_instance *eci) +{ + + exec_store(fd, eci, false); + + exec_store(fd, eci, true); + + run_spinner(fd, eci); +} + igt_main { struct drm_xe_engine_class_instance *hwe; @@ -343,6 +495,12 @@ igt_main xe_for_each_engine_class(class) xe_spin_fixed_duration(fd, gt, class, SPIN_FIX_DURATION_PREEMPT); + igt_subtest_with_dynamic("spin-timestamp-check") + xe_for_each_engine(fd, hwe) { + igt_dynamic_f("engine-%s", xe_engine_class_string(hwe->engine_class)) + xe_spin_timestamp_check(fd, hwe); + } + igt_fixture drm_close_driver(fd); } -- 2.34.1