From: "Jesse.zhang@amd.com" <jesse.zhang@amd.com>
To: <igt-dev@lists.freedesktop.org>
Cc: Vitaly Prosyak <vitaly.prosyak@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Christian Koenig <christian.koenig@amd.com>,
Kamil Konieczny <kamil.konieczny@linux.intel.com>,
"Jesse.zhang@amd.com" <Jesse.zhang@amd.com>,
Jesse Zhang <Jesse.Zhang@amd.com>
Subject: [PATCH i-g-t 3/4] tests/amd_deadlock: add the filter for amd deadlock
Date: Thu, 7 Nov 2024 10:05:09 +0800 [thread overview]
Message-ID: <20241107020510.350132-3-jesse.zhang@amd.com> (raw)
In-Reply-To: <20241107020510.350132-1-jesse.zhang@amd.com>
From: "Jesse.zhang@amd.com" <Jesse.zhang@amd.com>
Check sysfs reset mask before enabling certain subtests.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
---
tests/amdgpu/amd_deadlock.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/tests/amdgpu/amd_deadlock.c b/tests/amdgpu/amd_deadlock.c
index b5d053663..b8bb053ca 100644
--- a/tests/amdgpu/amd_deadlock.c
+++ b/tests/amdgpu/amd_deadlock.c
@@ -71,7 +71,8 @@ igt_main
igt_describe("Test-GPU-reset-by-access-gfx-illegal-reg");
igt_subtest_with_dynamic("amdgpu-gfx-illegal-reg-access") {
- if (arr_cap[AMD_IP_GFX]) {
+ if (arr_cap[AMD_IP_GFX] &&
+ is_reset_enable(AMD_IP_GFX, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-illegal-reg-access")
bad_access_ring_helper(device, CMD_STREAM_TRANS_BAD_REG_ADDRESS,
AMDGPU_HW_IP_GFX);
@@ -80,7 +81,8 @@ igt_main
igt_describe("Test-GPU-reset-by-access-gfx-illegal-mem-addr");
igt_subtest_with_dynamic("amdgpu-gfx-illegal-mem-access") {
- if (arr_cap[AMD_IP_GFX]) {
+ if (arr_cap[AMD_IP_GFX] &&
+ is_reset_enable(AMD_IP_GFX, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-illegal-mem-access")
bad_access_ring_helper(device, CMD_STREAM_TRANS_BAD_MEM_ADDRESS,
AMDGPU_HW_IP_GFX);
@@ -98,9 +100,11 @@ igt_main
igt_describe("Test-GPU-reset-by-access-compute-illegal-mem-addr");
igt_subtest("amdgpu-compute-illegal-mem-access") {
- igt_skip_on_f(!arr_cap[AMD_IP_COMPUTE], "SKIP, compute ring don't support\n");
+ if (arr_cap[AMD_IP_COMPUTE] &&
+ is_reset_enable(AMD_IP_COMPUTE, AMDGPU_RESET_TYPE_PER_QUEUE)) {
bad_access_ring_helper(device, CMD_STREAM_TRANS_BAD_MEM_ADDRESS,
AMDGPU_HW_IP_COMPUTE);
+ }
}
igt_describe("Test-GPU-reset-by-flooding-compute-ring-with-jobs");
@@ -113,7 +117,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-corrupted-header-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-corrupted-header-test") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-corrupted-header-test")
amdgpu_hang_sdma_ring_helper(device, DMA_CORRUPTED_HEADER_HANG);
}
@@ -121,7 +126,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-slow-linear-copy-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-slow-linear-copy") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-slow-linear-copy")
amdgpu_hang_sdma_ring_helper(device, DMA_SLOW_LINEARCOPY_HANG);
}
@@ -129,7 +135,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-badop-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-badop-test") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-badop-test")
bad_access_ring_helper(device, CMD_STREAM_EXEC_INVALID_OPCODE,
AMDGPU_HW_IP_DMA);
@@ -138,7 +145,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-bad-mem-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-bad-mem-test") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-bad-mem-test")
bad_access_ring_helper(device, CMD_STREAM_TRANS_BAD_MEM_ADDRESS,
AMDGPU_HW_IP_DMA);
@@ -147,7 +155,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-bad-reg-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-bad-reg-test") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-bad-reg-test")
bad_access_ring_helper(device, CMD_STREAM_TRANS_BAD_REG_ADDRESS,
AMDGPU_HW_IP_DMA);
@@ -156,7 +165,8 @@ igt_main
igt_describe("Test-GPU-reset-by-sdma-bad-length-with-jobs");
igt_subtest_with_dynamic("amdgpu-deadlock-sdma-bad-length-test") {
- if (arr_cap[AMD_IP_DMA]) {
+ if (arr_cap[AMD_IP_DMA] &&
+ is_reset_enable(AMD_IP_DMA, AMDGPU_RESET_TYPE_PER_QUEUE)) {
igt_dynamic_f("amdgpu-deadlock-sdma-bad-length-test")
bad_access_ring_helper(device, CMD_STREAM_EXEC_INVALID_PACKET_LENGTH,
AMDGPU_HW_IP_DMA);
--
2.25.1
next prev parent reply other threads:[~2024-11-07 2:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-07 2:05 [PATCH i-g-t 1/4] lib/amdgpu: add gpu reset check Jesse.zhang@amd.com
2024-11-07 2:05 ` [PATCH i-g-t 2/4] tests/amd_queue_reset: modify the asic filter Jesse.zhang@amd.com
2024-11-07 2:05 ` Jesse.zhang@amd.com [this message]
2024-11-07 2:05 ` [PATCH i-g-t 4/4] tests/amd_dispatch: add the filter for amd dispatch Jesse.zhang@amd.com
2024-11-11 0:44 ` vitaly prosyak
2024-11-07 2:54 ` ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/4] lib/amdgpu: add gpu reset check Patchwork
2024-11-07 3:02 ` ✓ CI.xeBAT: " Patchwork
2024-11-07 3:56 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-11-08 9:08 ` ✗ CI.xeFULL: " Patchwork
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