[PATCH v5 4/4] lib/gpgpu_shader: add support for Xe3 platforms

[Andrzej Hajda <andrzej.hajda@intel.com>]

System routine (SIP) on Xe3 platforms disallow indirect load/store
addressing. Surface descriptor must be passed in 2DBlock payload.
Use for it inline data passed from thread dispatcher.

v4:
  - moved gpgpu_alloc_gpu_addr changes to previous patch (Dominik)
v5:
  - make the requirement in the description more precise (Dominik)
  - removed extra lines from macro file (Dominik)

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
---
 lib/iga64_generated_codes.c | 13 ++++++++-----
 lib/iga64_macros.h          | 32 ++++++++++++++++++++++++++++----
 2 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index 96126b8c50c2..e1f68c968645 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,7 +3,7 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS 3534731658223b1594f68ca427687773
+#define MD5_SUM_IGA64_ASMS f0c9d803408104207f0427e387a8050c
 
 struct iga64_template const iga64_code_gpgpu_fill[] = {
 	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
@@ -118,10 +118,11 @@ struct iga64_template const iga64_code_write_a64_d32[] = {
 };
 
 struct iga64_template const iga64_code_end_system_routine_step_if_eq[] = {
-	{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
+	{ .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
 		0x80000966, 0x80018220, 0x02008000, 0x00008000,
 		0x80000965, 0x80118220, 0x02008010, 0xc0ded000,
 		0x800c0961, 0x1e054220, 0x00000000, 0x00000000,
+		0x80000061, 0x1e554220, 0x00000000, 0x00000000,
 		0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
 		0x80000061, 0x1e754220, 0x00000000, 0x00000003,
 		0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
@@ -522,13 +523,14 @@ struct iga64_template const iga64_code_media_block_write_aip[] = {
 };
 
 struct iga64_template const iga64_code_common_target_write[] = {
-	{ .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
+	{ .gen_ver = 2000, .size = 52, .code = (const uint32_t []) {
 		0x80100061, 0x1f054220, 0x00000000, 0x00000000,
 		0x80000061, 0x1f054220, 0x00000000, 0xc0ded001,
 		0x80000061, 0x1f154220, 0x00000000, 0xc0ded002,
 		0x80000061, 0x1f254220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x1f354220, 0x00000000, 0xc0ded004,
 		0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
+		0x80000061, 0x1e554220, 0x00000000, 0x00000000,
 		0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
 		0x80000061, 0x1e754220, 0x00000000, 0x0000000f,
 		0x80032031, 0x00000000, 0xd00e1e94, 0x04000000,
@@ -650,14 +652,15 @@ struct iga64_template const iga64_code_clear_r40[] = {
 };
 
 struct iga64_template const iga64_code_jump_dw_neq[] = {
-	{ .gen_ver = 2000, .size = 32, .code = (const uint32_t []) {
+	{ .gen_ver = 2000, .size = 36, .code = (const uint32_t []) {
 		0x800c0061, 0x1e054220, 0x00000000, 0x00000000,
+		0x80000061, 0x1e554220, 0x00000000, 0x00000000,
 		0x80000061, 0x1e654220, 0x00000000, 0xc0ded000,
 		0x80000061, 0x1e754220, 0x00000000, 0x00000003,
 		0x80032031, 0x1f0c0000, 0xd0061e8c, 0x04000000,
 		0x80000061, 0x30014220, 0x00000000, 0x00000000,
 		0x80008070, 0x00018220, 0x22001f04, 0xc0ded001,
-		0x84000020, 0x00004000, 0x00000000, 0xffffffa0,
+		0x84000020, 0x00004000, 0x00000000, 0xffffff90,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
 	{ .gen_ver = 1270, .size = 40, .code = (const uint32_t []) {
diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
index 40b6338928e1..ac482e47c05e 100644
--- a/lib/iga64_macros.h
+++ b/lib/iga64_macros.h
@@ -21,6 +21,13 @@
 #define R0_TGIDY r0.6<0;1,0>:ud
 #define R0_FFTID r0.5<0;1,0>:ud
 
+/* Inline data from COMPUTE_WALKER*, Bspec: 47203, 73584
+ * Filled by __xe*_gpgpu_execfunc.
+ */
+#define R1_TGT_ADDRESS r1.0<0;1,0>:uq
+#define R1_TGT_WIDTH r1.2<0;1,0>:ud
+#define R1_TGT_HEIGHT r1.3<0;1,0>:ud
+
 #define SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width)	\
 (W)	mov (8)		dst.0<1>:ud	0x0:ud		;\
 (W)	mov (1)		dst.1<1>:ud	y		;\
@@ -35,13 +42,25 @@
 (W)	mov (1)		dst.2<1>:ud	(width - 1):ud		;\
 (W)	mov (1)		dst.4<1>:ud	R0_FFTID
 
+#if GEN_VER < 3000
+#define SET_SURFACE_DESC(dst)			\
+(W)	mov (8)		dst.0<1>:ud	0x0:ud
+#else
+#define SET_SURFACE_DESC(dst)					\
+(W)	mov (1)		dst.0<1>:uq	R1_TGT_ADDRESS		;\
+(W)	add (1)		dst.2<1>:ud	R1_TGT_WIDTH	-1:d	;\
+(W)	add (1)		dst.3<1>:ud	R1_TGT_HEIGHT	-1:d	;\
+(W)	add (1)		dst.4<1>:ud	R1_TGT_WIDTH	-1:d
+#endif
+
 #define SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width)	\
-(W)	mov (8)		dst.0<1>:ud	0x0:ud		;\
-(W)	mov (1)		dst.6<1>:ud	y		;\
+	SET_SURFACE_DESC(dst)					;\
+(W)	mov (1)		dst.5<1>:ud	0x0:ud			;\
+(W)	mov (1)		dst.6<1>:ud	y			;\
 (W)	mov (1)		dst.7<1>:ud	(width - 1):ud
 
-#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width)		\
-(W)	mov (8)		dst.0<1>:ud	0x0:ud			;\
+#define SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width)	\
+	SET_SURFACE_DESC(dst)					;\
 (W)	shl (1)		dst.5<1>:ud	R0_TGIDX	0x2:ud	;\
 (W)	add (1)		dst.5<1>:ud	dst.5<0;1,0>:ud	x:ud	;\
 (W)	add (1)		dst.6<1>:ud	R0_TGIDY	y	;\
@@ -55,8 +74,13 @@
 #else
 #define SET_SHARED_SPACE_ADDR(dst, y, width) SET_SHARED_MEDIA_A2DBLOCK_PAYLOAD(dst, y, width)
 #define SET_THREAD_SPACE_ADDR(dst, x, y, width) SET_THREAD_MEDIA_A2DBLOCK_PAYLOAD(dst, x, y, width)
+#if GEN_VER < 3000
 #define LOAD_SPACE_DW(dst, src) send.tgm (1)	dst	src	null:0	0x0	0x62100003
 #define STORE_SPACE_DW(dst, src) send.tgm (1)	null	dst	null:0	0x0	0x64000007
+#else
+#define LOAD_SPACE_DW(dst, src) send.ugm (1)	dst	src	null:0	0x0	0x2120003
+#define STORE_SPACE_DW(dst, src) send.ugm (1)	null	dst	src:1	0x0	0x2020007
+#endif
 #endif
 
 #endif

-- 
2.34.1