[i-g-t, 1/2] tests/i915/pm_rc6_residency: Replace waitboost with spinner and use sysfs to reach peak frequency

[sk.anirban@intel.com]

From: Sk Anirban <sk.anirban@intel.com>

Leverage IGT spinner to trigger frequency scaling and
set RPS minimum frequency to RP0 for achieving peak frequency.
This method replaces the existing waitboost mechanism used
to reach maximum frequency.

Signed-off-by: Sk Anirban <sk.anirban@intel.com>
---
 tests/intel/i915_pm_rc6_residency.c | 98 +++++++++++++++++++----------
 1 file changed, 66 insertions(+), 32 deletions(-)

diff --git a/tests/intel/i915_pm_rc6_residency.c b/tests/intel/i915_pm_rc6_residency.c
index 7942d46d3..b646e181f 100644
--- a/tests/intel/i915_pm_rc6_residency.c
+++ b/tests/intel/i915_pm_rc6_residency.c
@@ -290,17 +290,6 @@ static unsigned int measured_usleep(unsigned int usec)
 	return igt_nsec_elapsed(&ts);
 }
 
-static uint32_t batch_create(int fd)
-{
-	const uint32_t bbe = MI_BATCH_BUFFER_END;
-	uint32_t handle;
-
-	handle = gem_create(fd, 4096);
-	gem_write(fd, handle, 0, &bbe, sizeof(bbe));
-
-	return handle;
-}
-
 static int open_pmu(int i915, uint64_t config)
 {
 	int fd;
@@ -312,45 +301,80 @@ static int open_pmu(int i915, uint64_t config)
 	return fd;
 }
 
-#define WAITBOOST 0x1
+#define FREQUENT_BOOST 0x1
 #define ONCE 0x2
 
 static void sighandler(int sig)
 {
 }
 
-static void bg_load(int i915, uint32_t ctx_id, uint64_t engine_flags, unsigned int flags, unsigned long *ctl)
+static uint32_t get_freq(int dirfd, uint8_t id)
+{
+	uint32_t val;
+
+	igt_assert(igt_sysfs_rps_scanf(dirfd, id, "%u", &val) == 1);
+
+	return val;
+}
+
+static int set_freq(int dirfd, uint8_t id, uint32_t val)
+{
+	return igt_sysfs_rps_printf(dirfd, id, "%u", val);
+}
+
+static void bg_load(int i915, uint32_t ctx_id, uint64_t engine_flags,
+		    unsigned int flags, unsigned long *ctl, unsigned int gt)
 {
 	const bool has_execlists = intel_gen(intel_get_drm_devid(i915)) >= 8;
-	struct drm_i915_gem_exec_object2 obj = {
-		.handle = batch_create(i915),
-	};
-	struct drm_i915_gem_execbuffer2 execbuf = {
-		.buffers_ptr = to_user_pointer(&obj),
-		.buffer_count = 1,
-		.flags = engine_flags,
-		.rsvd1 = ctx_id,
-	};
 	struct sigaction act = {
 		.sa_handler = sighandler
 	};
+	uint32_t rpn, rp0;
+	int sys;
+
+	igt_require_gem(i915);
+	sys = igt_sysfs_open(i915);
+	igt_require(sys != -1);
+	rpn = get_freq(sys, RPS_RPn_FREQ_MHZ);
+	rp0 = get_freq(sys, RPS_RP0_FREQ_MHZ);
 
 	sigaction(SIGINT, &act, NULL);
 	do {
 		uint64_t submit, wait, elapsed;
 		struct timespec tv = {};
+		const intel_ctx_t *ctx;
+		igt_spin_t *spin;
+		uint64_t ahnd;
 
-		igt_nsec_elapsed(&tv);
+		ctx = intel_ctx_create_for_gt(i915, gt);
+		ahnd = get_reloc_ahnd(i915, ctx->id);
 
-		gem_execbuf(i915, &execbuf);
+		igt_nsec_elapsed(&tv);
+		spin = igt_spin_new(i915,
+				    .ahnd = ahnd,
+				    .ctx = ctx,
+				    .engine = engine_flags);
 		submit = igt_nsec_elapsed(&tv);
-		if (flags & WAITBOOST) {
-			gem_sync(i915, obj.handle);
+		if (flags & FREQUENT_BOOST) {
+			/* Set MIN freq to RP0 to achieve the peak freq */
+			igt_assert_lt(0, set_freq(sys, RPS_MIN_FREQ_MHZ, rp0));
+			igt_assert(gem_bo_busy(i915, spin->handle));
+
+			/* Restore the MIN freq back to default */
+			igt_assert_lt(0, set_freq(sys, RPS_MIN_FREQ_MHZ, rpn));
+			igt_spin_free(i915, spin);
+			gem_quiescent_gpu(i915);
+			put_ahnd(ahnd);
+			intel_ctx_destroy(i915, ctx);
 			if (flags & ONCE)
-				flags &= ~WAITBOOST;
+				flags &= ~FREQUENT_BOOST;
 		} else  {
-			while (gem_bo_busy(i915, obj.handle))
-				usleep(0);
+			igt_assert(gem_bo_busy(i915, spin->handle));
+			igt_assert_lt(0, set_freq(sys, RPS_MIN_FREQ_MHZ, rpn));
+			igt_spin_free(i915, spin);
+			gem_quiescent_gpu(i915);
+			put_ahnd(ahnd);
+			intel_ctx_destroy(i915, ctx);
 		}
 		wait = igt_nsec_elapsed(&tv);
 
@@ -398,8 +422,8 @@ static void rc6_idle(int i915, uint32_t ctx_id, uint64_t flags, unsigned int gt)
 		double power;
 	} phases[] = {
 		{ "normal", 0 },
-		{ "boost", WAITBOOST },
-		{ "once", WAITBOOST | ONCE },
+		{ "boost", FREQUENT_BOOST },
+		{ "once", FREQUENT_BOOST | ONCE },
 	};
 	struct power_sample sample[2];
 	unsigned long slept, cycles;
@@ -438,7 +462,7 @@ static void rc6_idle(int i915, uint32_t ctx_id, uint64_t flags, unsigned int gt)
 	for (int p = 0; p < ARRAY_SIZE(phases); p++) {
 		memset(done, 0, 2 * sizeof(*done));
 		igt_fork(child, 1) /* Setup up a very light load */
-			bg_load(i915, ctx_id, flags, phases[p].flags, done);
+			bg_load(i915, ctx_id, flags, phases[p].flags, done, gt);
 
 		igt_power_get_energy(&gpu, &sample[0]);
 		cycles = -READ_ONCE(done[1]);
@@ -605,6 +629,11 @@ igt_main
 		i915 = drm_open_driver(DRIVER_INTEL);
 	}
 
+	igt_fixture
+	{
+		intel_allocator_multiprocess_start();
+	}
+
 	igt_subtest_with_dynamic("rc6-idle") {
 		const struct intel_execution_engine2 *e;
 
@@ -623,6 +652,11 @@ igt_main
 		}
 	}
 
+	igt_fixture
+	{
+		intel_allocator_multiprocess_stop();
+	}
+
 	igt_subtest_with_dynamic("rc6-fence") {
 		igt_require_gem(i915);
 		gem_quiescent_gpu(i915);
-- 
2.34.1