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From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com,
	jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com,
	matthew.brost@intel.com, jianxun.zhang@intel.com,
	shuicheng.lin@intel.com
Subject: [PATCH 4/4] tests/intel/xe_vm: Test DRM_IOCTL_XE_VM_GET_FAULTS fault reporting
Date: Mon, 10 Mar 2025 21:03:43 +0000	[thread overview]
Message-ID: <20250310210343.204246-5-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20250310210343.204246-1-jonathan.cavitt@intel.com>

Add a test to xe_vm that determines if pagefaults are correctly tracked
and reported to the struct drm_xe_vm_get_faults.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
 tests/intel/xe_vm.c | 177 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 177 insertions(+)

diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
index 40928b441c..a841c2a877 100644
--- a/tests/intel/xe_vm.c
+++ b/tests/intel/xe_vm.c
@@ -2359,6 +2359,10 @@ static void invalid_vm_id(int fd)
  * SUBTEST: vm-get-faults-invalid-fault-count
  * Functionality: ioctl_input_validation
  * Description: Check query with invalid fault_count returns expected error code
+ *
+ * SUBTEST: vm-get-faults-exercise
+ * Functionality: drm_xe_vm_get_faults
+ * Description: Check query correctly reports pagefaults on vm
  */
 static void get_faults_invalid_reserved(int fd, uint32_t vm)
 {
@@ -2396,6 +2400,178 @@ static void get_faults_invalid_fault_count(int fd, uint32_t vm)
 	do_ioctl_err(fd, DRM_IOCTL_XE_VM_GET_FAULTS, &query, EINVAL);
 }
 
+static void gen_pf(int fd, uint32_t vm, struct drm_xe_engine_class_instance *eci)
+{
+	uint64_t addr = 0x1a0000;
+	uint64_t sync_addr = 0x101a0000;
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		  .timeline_value = USER_FENCE_VALUE },
+	};
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(sync),
+	};
+	uint32_t exec_queues[1];
+	uint32_t bind_exec_queues[1];
+	size_t bo_size, sync_size;
+	struct {
+		uint32_t batch[16];
+		uint64_t pad;
+		uint64_t vm_sync;
+		uint32_t data;
+	} *data;
+	uint64_t *exec_sync;
+	int i, b;
+	int map_fd = -1;
+	int n_exec_queues = 1;
+	int n_execs = 64;
+
+	bo_size = sizeof(*data) * n_execs;
+	bo_size = xe_bb_size(fd, bo_size);
+	sync_size = sizeof(*exec_sync) * n_execs;
+	sync_size = xe_bb_size(fd, sync_size);
+
+#define	MAP_ADDRESS	0x00007fadeadbe000
+	data = mmap((void *)MAP_ADDRESS, bo_size, PROT_READ |
+		    PROT_WRITE, MAP_SHARED | MAP_FIXED |
+		    MAP_ANONYMOUS, -1, 0);
+	igt_assert(data != MAP_FAILED);
+	memset(data, 0, bo_size);
+
+#define EXEC_SYNC_ADDRESS	0x00007fbdeadbe000
+	exec_sync = mmap((void *)EXEC_SYNC_ADDRESS, sync_size, PROT_READ | PROT_WRITE,
+			MAP_SHARED | MAP_FIXED | MAP_ANONYMOUS, -1, 0);
+	igt_assert(exec_sync != MAP_FAILED);
+	memset(exec_sync, 0, sync_size);
+
+	for (i = 0; i < n_exec_queues; i++) {
+		exec_queues[i] = xe_exec_queue_create(fd, vm, eci, 0);
+		bind_exec_queues[i] = 0;
+	}
+
+	sync[0].addr = to_user_pointer(&data[0].vm_sync);
+	xe_vm_bind_userptr_async(fd, vm, bind_exec_queues[0],
+				 to_user_pointer(data), addr,
+				 bo_size, sync, 1);
+
+	xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE,
+		       bind_exec_queues[0], NSEC_PER_SEC);
+	data[0].vm_sync = 0;
+
+	xe_vm_bind_userptr_async(fd, vm, bind_exec_queues[0],
+				 to_user_pointer(exec_sync), sync_addr,
+				 sync_size, sync, 1);
+	xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE,
+		       bind_exec_queues[0], NSEC_PER_SEC);
+	data[0].vm_sync = 0;
+
+	for (i = 0; i < n_execs; i++) {
+		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
+		uint64_t batch_addr = addr + batch_offset;
+		uint64_t sdi_offset = (char *)&data[i].data - (char *)data;
+		uint64_t sdi_addr = addr + sdi_offset;
+		int e = i % n_exec_queues;
+
+		b = 0;
+
+		data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		data[i].batch[b++] = sdi_addr;
+		data[i].batch[b++] = sdi_addr >> 32;
+		data[i].batch[b++] = 0xc0ffee;
+		data[i].batch[b++] = MI_BATCH_BUFFER_END;
+		igt_assert(b <= ARRAY_SIZE(data[i].batch));
+
+		sync[0].addr = sync_addr + (char *)&exec_sync[i] - (char *)exec_sync;
+
+		exec.exec_queue_id = exec_queues[e];
+		exec.address = batch_addr;
+		xe_exec(fd, &exec);
+
+		if (i + 1 != n_execs) {
+			/*
+			 * Wait for exec completion and check data as
+			 * userptr will likely change to different
+			 * physical memory on next mmap call triggering
+			 * an invalidate.
+			 */
+			xe_wait_ufence(fd, &exec_sync[i],
+				       USER_FENCE_VALUE, exec_queues[e],
+				       NSEC_PER_SEC);
+			igt_assert_eq(data[i].data, 0xc0ffee);
+			data = mmap((void *)MAP_ADDRESS, bo_size,
+				    PROT_READ | PROT_WRITE, MAP_SHARED |
+				    MAP_FIXED | MAP_ANONYMOUS, -1, 0);
+			igt_assert(data != MAP_FAILED);
+		}
+	}
+
+	for (i = n_execs - 1; i < n_execs; i++) {
+		int64_t timeout = NSEC_PER_SEC;
+
+		igt_assert_eq(__xe_wait_ufence(fd, &exec_sync[i], USER_FENCE_VALUE,
+					       exec_queues[i % n_exec_queues], &timeout), 0);
+	}
+
+	sync[0].addr = to_user_pointer(&data[0].vm_sync);
+	data[0].vm_sync = 0;
+	xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, sync_addr, sync_size,
+			   sync, 1);
+	xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE,
+		       bind_exec_queues[0], NSEC_PER_SEC);
+	data[0].vm_sync = 0;
+	xe_vm_unbind_async(fd, vm, bind_exec_queues[0], 0, addr, bo_size,
+			   sync, 1);
+	xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE,
+		       bind_exec_queues[0], NSEC_PER_SEC);
+
+	for (i = 0; i < n_exec_queues; i++) {
+		xe_exec_queue_destroy(fd, exec_queues[i]);
+		if (bind_exec_queues[i])
+			xe_exec_queue_destroy(fd, bind_exec_queues[i]);
+	}
+
+	munmap(exec_sync, sync_size);
+	if (map_fd != -1)
+		close(map_fd);
+}
+
+static void get_faults_exercise(int fd, uint32_t vm)
+{
+	struct drm_xe_engine_class_instance *hwe;
+	struct xe_vm_fault *faults, f0, f;
+	struct drm_xe_vm_get_faults query = {0};
+	int i;
+
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_GET_FAULTS, &query), 0);
+
+	igt_assert_eq(query.size, 0);
+	igt_assert_eq(query.fault_count, 0);
+
+	xe_for_each_engine(fd, hwe)
+		gen_pf(fd, vm, hwe);
+
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_GET_FAULTS, &query), 0);
+	igt_assert_lt(0, query.size);
+	igt_assert_eq(query.size, query.fault_count / sizeof(struct xe_vm_fault));
+
+	faults = malloc(query.size);
+	igt_assert(faults);
+
+	query.faults = to_user_pointer(faults);
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_GET_FAULTS, &query), 0);
+
+	f0 = faults[0];
+	for (i = 0; i < query.fault_count; i++) {
+		f = faults[i];
+		igt_assert_eq(f.address, f0.address);
+		igt_assert_eq(f.address_type, f0.address_type);
+		igt_assert_eq(f.address_precision, f0.address_precision);
+	}
+}
+
 static void test_get_faults(int fd, void (*func)(int fd, uint32_t vm))
 {
 	uint32_t vm;
@@ -2526,6 +2702,7 @@ igt_main
 		{ "invalid-vm-id", get_faults_invalid_vm_id },
 		{ "invalid-size", get_faults_invalid_size },
 		{ "invalid-fault-count", get_faults_invalid_fault_count },
+		{ "exercise", get_faults_exercise },
 		{ }
 	};
 
-- 
2.43.0


  parent reply	other threads:[~2025-03-10 21:03 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-10 21:03 [PATCH 0/4] tests/intel/xe_vm: Add drm_xe_vm_get_faults tests Jonathan Cavitt
2025-03-10 21:03 ` [PATCH 1/4] drm-uapi/xe: Declare xe_vm_get_faults_ioctl Jonathan Cavitt
2025-03-10 21:03 ` [PATCH 2/4] lib/xe/xe_ioctl: Add xe_vm_get_faults helper function Jonathan Cavitt
2025-03-10 21:03 ` [PATCH 3/4] tests/intel/xe_vm: Add DRM_IOCTL_XE_VM_GET_FAULTS validation tests Jonathan Cavitt
2025-03-10 21:03 ` Jonathan Cavitt [this message]
2025-03-11  3:28 ` ✓ Xe.CI.BAT: success for tests/intel/xe_vm: Add drm_xe_vm_get_faults tests Patchwork
2025-03-11  3:46 ` ✓ i915.CI.BAT: " Patchwork
2025-03-11  5:55 ` ✗ i915.CI.Full: failure " Patchwork
2025-03-11 23:33 ` ✗ Xe.CI.Full: " Patchwork

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