From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A236C36014 for ; Fri, 28 Mar 2025 08:24:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF9FA10E9A5; Fri, 28 Mar 2025 08:24:47 +0000 (UTC) Received: from rtg-sunil-navi33.amd.com (unknown [165.204.156.251]) by gabe.freedesktop.org (Postfix) with ESMTPS id 57AA310E9A6 for ; Fri, 28 Mar 2025 08:24:38 +0000 (UTC) Received: from rtg-sunil-navi33.amd.com (localhost [127.0.0.1]) by rtg-sunil-navi33.amd.com (8.15.2/8.15.2/Debian-22ubuntu3) with ESMTP id 52S8OXGx1470052; Fri, 28 Mar 2025 13:54:33 +0530 Received: (from sunil@localhost) by rtg-sunil-navi33.amd.com (8.15.2/8.15.2/Submit) id 52S8OXX31470051; Fri, 28 Mar 2025 13:54:33 +0530 From: Sunil Khatri To: igt-dev@lists.freedesktop.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Vitaly Prosyak , Sunil Khatri Subject: [PATCH v3 15/19] lib/amdgpu: use a memory fence to serialize write Date: Fri, 28 Mar 2025 13:54:12 +0530 Message-Id: <20250328082416.1469810-15-sunil.khatri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250328082416.1469810-1-sunil.khatri@amd.com> References: <20250328082416.1469810-1-sunil.khatri@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Use a memory fence to serialize all the writes in the queue before updating wptr and ringing the doorbell This ensures memory is written in same sequence as intended to. Signed-off-by: Sunil Khatri --- lib/amdgpu/amd_user_queue.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c index d1763f5d6..0235b07ac 100644 --- a/lib/amdgpu/amd_user_queue.c +++ b/lib/amdgpu/amd_user_queue.c @@ -148,8 +148,17 @@ void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_co /* empty dword is needed for fence signal pm4 */ amdgpu_pkt_add_dw(0); +#if DETECT_CC_GCC && (DETECT_ARCH_X86 || DETECT_ARCH_X86_64) + asm volatile ("mfence" : : : "memory"); +#endif + + /* Below call update the wptr address so will wait till all writes are completed */ amdgpu_pkt_end(); +#if DETECT_CC_GCC && (DETECT_ARCH_X86 || DETECT_ARCH_X86_64) + asm volatile ("mfence" : : : "memory"); +#endif + /* Update the door bell */ ring_context->doorbell_cpu[DOORBELL_INDEX] = *ring_context->wptr_cpu; -- 2.43.0