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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2025 02:29:34.8947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c79958f5-9d14-490b-3548-08dd7e20dbee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7188 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" From: "Jesse.zhang@amd.com" This patch adds support for queue priority levels and secure queue creation flags in the user queue interface. The changes include: 1. Extended the amdgpu_ring_context struct to store queue priority 2. Modified amdgpu_user_queue_create() to: - Parse and pass through priority flags from context - Handle secure queue flag - Include flags in queue creation IOCTL calls The priority levels allow workloads to specify different scheduling priorities, with HIGH priority restricted to admin-only use. The secure flag enables creation of queues that can access protected content. This matches the corresponding libdrm changes in commit fdf384d4b546 ("amdgpu: add priority and secure flags for user queues"). add both the conditions under one if (ctxt->secure) (Sunil) Signed-off-by: Jesse.Zhang Reviewed-by: Sunil Khatri --- lib/amdgpu/amd_ip_blocks.h | 1 + lib/amdgpu/amd_user_queue.c | 16 +++++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h index 231098eb8..7d48f9107 100644 --- a/lib/amdgpu/amd_ip_blocks.h +++ b/lib/amdgpu/amd_ip_blocks.h @@ -118,6 +118,7 @@ struct amdgpu_ring_context { uint32_t *pm4; /* data of the packet */ uint32_t pm4_size; /* max allocated packet size */ bool secure; /* secure or not */ + uint32_t priority; /* user queue priority */ uint64_t bo_mc; /* GPU address of first buffer */ uint64_t bo_mc2; /* GPU address for p4 packet */ diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c index 0cdd0c4f9..444f9c022 100644 --- a/lib/amdgpu/amd_user_queue.c +++ b/lib/amdgpu/amd_user_queue.c @@ -270,7 +270,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ unsigned int type) { int r; - uint64_t gtt_flags = 0; + uint64_t gtt_flags = 0, queue_flags = 0; struct drm_amdgpu_userq_mqd_gfx11 gfx_mqd; struct drm_amdgpu_userq_mqd_sdma_gfx11 sdma_mqd; struct drm_amdgpu_userq_mqd_compute_gfx11 compute_mqd; @@ -281,8 +281,14 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ return; } - if (ctxt->secure) + if (ctxt->secure) { gtt_flags |= AMDGPU_GEM_CREATE_ENCRYPTED; + queue_flags |= AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; + } + + if (ctxt->priority) + queue_flags |= ctxt->priority & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK; + r = amdgpu_query_uq_fw_area_info(device_handle, AMD_IP_GFX, 0, &ctxt->info); igt_assert_eq(r, 0); @@ -404,7 +410,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ ctxt->db_handle, DOORBELL_INDEX, ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE, ctxt->wptr.mc_addr, ctxt->rptr.mc_addr, - mqd, &ctxt->queue_id); + mqd, queue_flags, &ctxt->queue_id); igt_assert_eq(r, 0); break; @@ -413,7 +419,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ ctxt->db_handle, DOORBELL_INDEX, ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE, ctxt->wptr.mc_addr, ctxt->rptr.mc_addr, - mqd, &ctxt->queue_id); + mqd, queue_flags, &ctxt->queue_id); igt_assert_eq(r, 0); break; @@ -422,7 +428,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_ ctxt->db_handle, DOORBELL_INDEX, ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE, ctxt->wptr.mc_addr, ctxt->rptr.mc_addr, - mqd, &ctxt->queue_id); + mqd, queue_flags, &ctxt->queue_id); igt_assert_eq(r, 0); break; -- 2.25.1