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d="scan'208";a="184941242" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.244.157]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2025 03:42:43 -0700 From: Kamil Konieczny To: igt-dev@lists.freedesktop.org Cc: Kamil Konieczny , Matt Roper , Gustavo Sousa , Jani Nikula , Shekhar Chauhan , Lucas De Marchi Subject: [PATCH i-g-t v2 1/1] lib/pciids: Add NVL-S and split out BMG-G21 Date: Tue, 28 Oct 2025 11:42:34 +0100 Message-ID: <20251028104234.14745-2-kamil.konieczny@linux.intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028104234.14745-1-kamil.konieczny@linux.intel.com> References: <20251028104234.14745-1-kamil.konieczny@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Sync with drm-next kernel commit c002b1764e7b ("drm/xe/nvl: Define NVL-S platform") Link: https://lore.kernel.org/r/20251016-xe3p-v3-11-3dd173a3097a@intel.com This adds NovaLake-S PCI ids, and with it there are two more PCI ids commits, one for splitting BMG-G21 out of BMG for workarounds and the other adds a kernel macro. 78de8f876683 ("drm/xe: Handle Wa_22010954014 and Wa_14022085890 as device workarounds") Link: https://lore.kernel.org/r/20251013200944.2499947-40-matthew.d.roper@intel.com edb660ad79ff ("drm/intel/pciids: Add match on vendor/id only") Link: https://lore.kernel.org/r/20250808-intel-pci-device-v1-1-ce3545d86502@intel.com v2: squashed into one commit (Lucas) Cc: Matt Roper Cc: Gustavo Sousa Cc: Jani Nikula Cc: Shekhar Chauhan Cc: Lucas De Marchi Signed-off-by: Kamil Konieczny --- lib/pciids.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/lib/pciids.h b/lib/pciids.h index 76f8d26f9..9f095a99d 100644 --- a/lib/pciids.h +++ b/lib/pciids.h @@ -26,6 +26,11 @@ #define __PCIIDS_H__ #ifdef __KERNEL__ +#define INTEL_PCI_DEVICE(_id, _info) { \ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \ + .driver_data = (kernel_ulong_t)(_info), \ +} + #define INTEL_VGA_DEVICE(_id, _info) { \ PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \ .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \ @@ -844,7 +849,7 @@ MACRO__(0x64B0, ## __VA_ARGS__) /* BMG */ -#define INTEL_BMG_IDS(MACRO__, ...) \ +#define INTEL_BMG_G21_IDS(MACRO__, ...) \ MACRO__(0xE202, ## __VA_ARGS__), \ MACRO__(0xE209, ## __VA_ARGS__), \ MACRO__(0xE20B, ## __VA_ARGS__), \ @@ -853,7 +858,10 @@ MACRO__(0xE210, ## __VA_ARGS__), \ MACRO__(0xE211, ## __VA_ARGS__), \ MACRO__(0xE212, ## __VA_ARGS__), \ - MACRO__(0xE216, ## __VA_ARGS__), \ + MACRO__(0xE216, ## __VA_ARGS__) + +#define INTEL_BMG_IDS(MACRO__, ...) \ + INTEL_BMG_G21_IDS(MACRO__, __VA_ARGS__), \ MACRO__(0xE220, ## __VA_ARGS__), \ MACRO__(0xE221, ## __VA_ARGS__), \ MACRO__(0xE222, ## __VA_ARGS__), \ @@ -876,4 +884,13 @@ MACRO__(0xFD80, ## __VA_ARGS__), \ MACRO__(0xFD81, ## __VA_ARGS__) +/* NVL-S */ +#define INTEL_NVLS_IDS(MACRO__, ...) \ + MACRO__(0xD740, ## __VA_ARGS__), \ + MACRO__(0xD741, ## __VA_ARGS__), \ + MACRO__(0xD742, ## __VA_ARGS__), \ + MACRO__(0xD743, ## __VA_ARGS__), \ + MACRO__(0xD744, ## __VA_ARGS__), \ + MACRO__(0xD745, ## __VA_ARGS__) + #endif /* __PCIIDS_H__ */ -- 2.51.1