[PATCH v2 3/4] tests/intel/xe_pat: add bo-wb-comp-1way-bind subtest

[Xin Wang <x.wang@intel.com>]

Add a xe_pat subtest that looks up a WB+compression+1way PAT entry
from the debugfs PAT table and validates that binding a WB-cached
BO with that PAT index succeeds on Xe3+.

Skip the test when the platform doesn't expose a suitable PAT entry.

Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
---
 tests/intel/xe_pat.c | 91 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 8af6ad174..79d0e7198 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -112,6 +112,43 @@ static int xe_fetch_pat_sw_config(int fd, struct intel_pat_cache *pat_sw_config)
 	return parsed;
 }
 
+static bool find_wb_comp_1way_pat_index(int fd, uint8_t *pat_index_out)
+{
+	struct intel_pat_cache pat_sw_config = {};
+	int32_t parsed;
+	int i;
+
+	parsed = xe_fetch_pat_sw_config(fd, &pat_sw_config);
+
+	for (i = 0; i < parsed; i++) {
+		uint32_t pat = pat_sw_config.entries[i].pat;
+
+		if (pat_sw_config.entries[i].rsvd)
+			continue;
+
+		if (!(pat & XE2_COMP_EN))
+			continue;
+
+		if (REG_FIELD_GET(XE2_COH_MODE, pat) != COH_MODE_1WAY)
+			continue;
+
+		if (REG_FIELD_GET(XE2_L3_POLICY, pat) != L3_CACHE_POLICY_WB)
+			continue;
+
+		/*
+		 * Matches Xe3 compressed+coherent entry (see kernel xe3_lpg_pat_table[16]).
+		 * Note: L4 policy is UC in that entry.
+		 */
+		if (REG_FIELD_GET(XE2_L4_POLICY, pat) != L4_CACHE_POLICY_UC)
+			continue;
+
+		*pat_index_out = i;
+		return true;
+	}
+
+	return false;
+}
+
 /**
  * SUBTEST: pat-sanity
  * Test category: functionality test
@@ -958,6 +995,42 @@ static void bo_comp_disable_bind(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+/**
+ * SUBTEST: bo-wb-comp-1way-bind
+ * Test category: functionality test
+ * Description: Validate binding a WB-cached BO using a WB+compression+1way PAT
+ * index (as advertised by the debugfs PAT table) succeeds. Skip if the
+ * platform doesn't expose such a PAT entry.
+ */
+static void bo_wb_comp_1way_bind(int fd)
+{
+	size_t size = xe_get_default_alignment(fd);
+	uint16_t dev_id = intel_get_drm_devid(fd);
+	uint8_t wb_comp_pat_index;
+	bool supported;
+	uint32_t vm, bo;
+	int ret;
+
+	igt_require(intel_get_device_info(dev_id)->graphics_ver >= 30);
+
+	supported = find_wb_comp_1way_pat_index(fd, &wb_comp_pat_index);
+	igt_require_f(supported, "No WB+compression+1way PAT index found, skipping.\n");
+
+	vm = xe_vm_create(fd, 0, 0);
+	bo = xe_bo_create_caching(fd, 0, size, system_memory(fd), 0,
+				  DRM_XE_GEM_CPU_CACHING_WB);
+
+	ret = __xe_vm_bind(fd, vm, 0, bo, 0, 0x100000,
+			  size, 0, 0, NULL, 0,
+			  0, wb_comp_pat_index, 0);
+
+	igt_assert_eq(ret, 0);
+	xe_vm_unbind_sync(fd, vm, 0, 0x100000, size);
+
+	gem_close(fd, bo);
+	xe_vm_destroy(fd, vm);
+}
+
 /**
  * SUBTEST: userptr-comp
  * Test category: functionality test
@@ -1230,6 +1303,18 @@ const struct pat_index_entry bmg_g21_pat_index_modes[] = {
 	{ NULL, 27, false, "c2-2way",     XE_COH_AT_LEAST_1WAY       },
 };
 
+const struct pat_index_entry xe3_lpg_pat_index_modes[] = {
+	XE_COMMON_PAT_INDEX_MODES,
+
+	/* Too many, just pick some of the interesting ones */
+	{ NULL, 1,  false, "1way",        XE_COH_AT_LEAST_1WAY       },
+	{ NULL, 2,  false, "2way",        XE_COH_AT_LEAST_1WAY       },
+	{ NULL, 2,  false, "2way-cpu-wc", XE_COH_AT_LEAST_1WAY, true },
+	{ NULL, 5,  false, "uc-1way",     XE_COH_AT_LEAST_1WAY       },
+	{ NULL, 12, true,  "uc-comp",     XE_COH_NONE                },
+	{ NULL, 16, true,  "wb-comp-2way",XE_COH_AT_LEAST_1WAY       },
+	{ NULL, 27, false, "c2-2way",     XE_COH_AT_LEAST_1WAY       },
+};
 /*
  * Depending on 2M/1G GTT pages we might trigger different PTE layouts for the
  * PAT bits, so make sure we test with and without huge-pages. Also ensure we
@@ -1461,6 +1546,9 @@ int igt_main_args("V", NULL, help_str, opt_handler, NULL)
 	igt_subtest("bo-comp-disable-bind")
 		bo_comp_disable_bind(fd);
 
+	igt_subtest("bo-wb-comp-1way-bind")
+		bo_wb_comp_1way_bind(fd);
+
 	igt_subtest_with_dynamic("pat-index-xelp") {
 		igt_require(intel_graphics_ver(dev_id) <= IP_VER(12, 55));
 		subtest_pat_index_modes_with_regions(fd, xelp_pat_index_modes,
@@ -1486,6 +1574,9 @@ int igt_main_args("V", NULL, help_str, opt_handler, NULL)
 		if (intel_graphics_ver(dev_id) == IP_VER(20, 1))
 			subtest_pat_index_modes_with_regions(fd, bmg_g21_pat_index_modes,
 							     ARRAY_SIZE(bmg_g21_pat_index_modes));
+		else if (intel_get_device_info(dev_id)->graphics_ver == 30)
+			subtest_pat_index_modes_with_regions(fd, xe3_lpg_pat_index_modes,
+							     ARRAY_SIZE(xe3_lpg_pat_index_modes));
 		else
 			subtest_pat_index_modes_with_regions(fd, xe2_pat_index_modes,
 							     ARRAY_SIZE(xe2_pat_index_modes));
-- 
2.43.0